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Operazionnie ysiliteli ,ZAP/AZP & (ïðîäîëæåíèå)
milstar: 1941: First (vacuum tube) op-amp An op-amp, defined as a general-purpose, DC-coupled, high gain, inverting feedback amplifier, is first found in US Patent 2,401,779 "Summing Amplifier" filed by Karl D. Swartzel Jr. of Bell labs in 1941. This design used three vacuum tubes to achieve a gain of 90dB and operated on voltage rails of ±350V. ###################################################### It had a single inverting input rather than differential inverting and non-inverting inputs, as are common in today's op-amps. Throughout World War II, Swartzel's design proved its value by being liberally used in the M9 artillery director designed at Bell Labs. ######################################################################### This artillery director worked with the SCR584 radar system to achieve extraordinary hit rates (near 90%) that ####################################################################### would not have been possible otherwise.[3] ########################### http://en.wikipedia.org/wiki/Operational_amplifier
milstar: https://www.edn.com/improving-high-speed-adc-harmonic-performance-for-unbuffered-adcs/
milstar: How fast is fast? The new ADC samples and digitizes spectrum signals at a rate of over 60 billion times per second (60 GigaSamples/sec). That’s fast enough to directly detect and analyze any signal at 30 GHz or below—a range that encompasses the vast majority of operating frequencies of interest https://www.darpa.mil/news-events/2016-01-11 https://www.businesswire.com/news/home/20140915006629/en/Semtech-Ultra-High-Speed-ADC-DAC-Advanced-Digital
milstar: https://www.iqanalog.com/news
milstar: 21102B–BDC–03/13EV10AS152Ae2v semiconductors SAS 20131. Block DiagramThe EV10AS152A combines a 10-bit 3 Gsps fully bipolar analog-to-digital converter chip, driving a fullybipolar DMUX chip with selectable Demultiplexing ratio (1:2) or (1:4). The 5 GHz full power inputbandwidth of the ADC allows the direct digitization of greater than 1 GHz broadband signals in the highIF region, in either L_Band or S_Band ------ but SFDR only 50-54 dbfs ###################### https://www.teledyne-e2v.com/resources/account/download-datasheet/1756
milstar: https://www.teledyne-e2v.com/shared/content/resources/File/documents/broadband-data-converters/EV12AS200A/EV12AS200AZP_DS.pdf 12 but 1.5gsps SFDR only 63-66dbfs
milstar: 14 bit 3 gsps ,but not space grate 0.022 micron 2600 mhz SFDR 70 dbfs input -2dbfs https://www.analog.com/media/en/technical-documentation/data-sheets/AD9208.pdf
milstar: The AD9213 achieves dynamic range and linearity performance while consuming <4.6 W typical. The device is based on an interleaved pipeline architecture and features a proprietary calibration and randomization technique that suppresses interleaving spurious artifacts into its noise floor 12 bit 10 gsps 1000mhz ,sfdr 70 dbfs input -1 dbfs,sinad -55.6 https://www.analog.com/media/en/technical-documentation/data-sheets/ad9213.pdf
milstar: 12 bit single chan 10 gsps 997 mhz -1dbfs sfdr 63 db sinad -53.5 http://www.ti.com/lit/ds/slvsen9/slvsen9.pdf
milstar: Figure 1 illustrates a high level overview of a typical current X-band radar system. Within this system, two analog mixing stages are typically utilized. https://www.analog.com/en/technical-articles/the-demand-for-digital.html# The first stage mixes the pulsed radar return to a frequency of around 1 GHz and the second to an IF in the region of 100 MHz to 200 MHz to enable sampling of the signal using a 200 MSPS or lower ADC, to a resolution of 12 bits or higher. The latest GSPS ADCs are able to provide in excess of 75 dBc SFDR, which is nearly a 20 dBc improvement over devices that have been available in the last decade. This significant leap is even more critical when competing with recent communications infrastructure frequency allocations. The next generation of GSPS converters, such as the AD9625, based on 65 nm or finer CMOS process geometries Radar waveform bandwidths can vary dramatically depending on the application. For example, some synthetic aperture imaging radar waveforms require hundreds of MHz while tracking radars may use wave forms that are tens of MHz wide or even less. For example, consider radar using a 30 MHz bandwidth waveform at an IF of 800 MHz. If this is sampled using an ADC at a sample rate of 2.0 GSPS to a resolution of 12 bits, the output bandwidth of the data would be 1000 MHz, far in excess of the signal bandwidth, and the output data rate from the converter would be 3.0 GBps. If the data is decimated by a factor of 16 using a DDC, not only does the decimation provide some increased noise reduction but the output data rate is reduced to below 625 MBps, which enables data transportation using only a single JESD204B lane!
milstar: https://www.sandia.gov/radar/files/spie_lynx.pdf The Analog-to-Digital Conversion (ADC) is also accomplished by a custom VME board that operates at 125 MHz andprovides 8-bit data. This data can be presummed and otherwise pre-processed before being sent across a RACEway bus to thesignal processor
milstar: https://www.sandia.gov/radar/imagery/index.html
milstar: Resolution 0.1 to 3.0m https://www.sandia.gov/RADAR/files/spie_lynx.pdf The Analog-to-Digital Conversion (ADC) is also accomplished by a custom VME board that operates at 125 MHz and provides 8-bit data. This data can be presummed and otherwise pre-processed before being sent across a RACE way bus to the signal processor http://read.pudn.com/downloads153/doc/673057/A%20Time-Transformation%20Technique.pdf Stretch:ATime-Transfor-mationTechnique Consider an experiment in which the rise timeassociated with a nonrepetitive nanosecond transientis to be mea-sured. If the signal is applied directly to the input of an oscilloscope,inefficient performance and cost results.This due to the factthatan expensive wide-band oscilloscope is required,despite the fact that the duration of the transient is short and the total information content is small.If we had aconvenientway of reducing the bandwidth of the signal by slowing down the waveform before the signal is displayed,we could use an inexpensive instrument.The purpose of this paper is to describe a technique that can be used to provide this function for a wide variety of applications. http://read.pudn.com/downloads153/doc/673057/A%20Time-Transformation%20Technique.pdf
milstar: The latest generation of Teledyne e2v’s ADC features a sampling rate of 5.4GSps (Giga samples per second), input bandwidth of 4.8GHz, low latency (26 clock cycles) ###################### https://www.teledyne-e2v.com/products/semiconductors/adc/ev12as350/ sfdr 1900mhz 58db,snr 53.2db power d. 6.7wt ###################### https://www.teledyne-e2v.com/shared/content/resources/File/documents/broadband-data-converters/EV12AS200A/EV12AS200AZP_DS.pdf Very Low Latency(<5ClockCycles) ######################## Fs 1.5 gsps ,12 bit SFDR 65 db 1600 mhz
milstar: As radio astronomy receiver bandwidth increases, it is nec-essary to increase the speed of analog-to-digital conversion(ADC) as well as the digital signal processing (DSP) in thetelescope’s back end. Otherwise a complex and expensivemixer-filter system is needed, to break the IF bandwidthinto smaller blocks for digital sampling and signal process-ing. Analog-to-digital converters (ADC) capable of samplerates five gigasamples-per-second and faster are now avail-able http://www.atrasc.com/content/stick/papers/ATRASC2018SummaryWeintroubv6.pdf In current wide-band instruments, usable bandwidth blocks∼2 GHz canbe processed digitally, and we envisage a near term futurewhere blocks∼10 GHz might be handled by a single com-pact module. This paper reviews ultra-wideband ADC andDSP technology, and describes examples of wideband pro-cessing in radio astronomy correlators and phased arrays In a sampled data system the width of a single block of pro-cessed bandwidth is set by the ADC sample rate throughthe Nyquist critereon. If the block is narrow, the processormust be preceded by an IF system with many channels; a socalled “hybrid” implementation, which, if large, is likely tobe cost-prohibitive. . FPGAs arenow equipped with asynchronous serializer-deserializer in-put output devices (SERDES). For the newestGTYseries ofSERDES included on the Xilinx Ultrascale+ family input-output data rates in excess of 30 gigabits-per-second (Gbps)is possible. An essential function of the SERDES is todemultiplexthe very high bitrate from the fast ADC chip,so that the FPGA, The numberof bits of conversion is also key, typically, though, singlecore fast devices have relatively few bits. We view four bitsas effectively the minimum requirements for current instru-ment development. In case of correlators four bits delivers99% digital efficiency.
milstar: https://books.google.de/books?id=Plc6pOgteF4C&pg=PA4&lpg=PA4&dq=ew+receiver+design&source=bl&ots=fXa7wCArTW&sig=ACfU3U0COUAdsYURs10h7dZYPMn_q4IXeg&hl=de&sa=X&ved=2ahUKEwiUyK3h15voAhUC3qQKHSWABvgQ6AEwC3oECAcQAQ#v=onepage&q=ew%20receiver%20design&f=false
milstar: As shown in Figure 9, assume that in band 2 we are looking for a 4.5 GHz signal that has a PRI of 1 kHz. Measurements are made at an IF of 3.5 GHz since LO-RF = IF = 8-4.5 = 3.5 GHz. If a 6.5 GHz signal is applied to band 3, its IF also equals 3.5 since LO-RF = 10-6.5 = 3.5 GHz. If this is a strong signal, has a PRI of 1 kHz, and there is switch leakage, a weak signal will be measured and processed when the switch is pointed to band 2. The receiver measures an IF of 3.5 GHz and since the switch is pointed to band 2, it scales the measured IF using the LO of band 2 i.e., LO-IF = RF = 8-3.5 = 4.5 GHz. Therefore, a 4.5 GHz signal is assumed to be measured when a 6.5 GHz signal is applied. Similarly this 6.5 GHz signal would appear as a weak 3.5 GHz signal from band 1 or a 9.5 GHz signal from band 4. https://www.rfcafe.com/references/electrical/ew-radar-handbook/receiver-tests.htm
milstar: https://rd.springer.com/article/10.1007/s10470-009-9422-7 The final post layout simulated system features an ENOB of 7.2-bits at an input frequency of 3.125 GHz and a sampling rate of 12.5 GS/s with a FOM of 12.9 pJ per conversion. Both DNL and INL are within 0.5 and 1 LSB, respectively. The converter occupies 10 mm2 and dissipates 14 W from a 3.3 V supply. The THA and the comparator, as the most critical building blocks affecting the overall performance of the ADC, were implemented experimentally and fully characterized in order to verify their performance and to ascertain the possibility of implementing the complete ADC. The THA occupies an area of 0.5 mm2. It features a SNDR of 47 dB or 7.5-bits ENOB for a 3 GHz bandwidth, a hold time of 21 ps with a droop rate of 11 mV/80 ps and a power dissipation of 230 mW from a 3.3 V supply. The comparator occupies an area of 0.38 mm2 and exhibits an input sensitivity of ±2 mV, an input offset voltage of 1.5 mV, latch and recovery times of 19 and 21 ps, respectively, and a power dissipation of 150 mW from a 3.3 V supply. The experimental results are in good agreement with simulation and expected specifications and indicate that both circuits are suitable for the implementation of the ADC and help to validate that the 8-bit 12.5 GS/s ADC is feasible for implementation in a 0.25 μm SiGe process. The requirement for several down-conversion stages is predicated by the limited bandwidth of the ADC. If a wide-bandwidth ADCs is available, a single down-conversion can be used, as illustrated in Fig. 2, thus improving the linearity of the receiver. Using such an approach, in a satellite communication system, a 64 QAM RF signal in the 10–30 GHz range can be down converted to the IF band of 1–3 GHz using only 1 mixing stage. In this case, the high-speed ADC must have an input bandwidth of 3 GHz with a typical resolution of 8 bits. Higher-order modulation schemes (such as 256 QAM) impose more stringent requirements on the SNR performance of the ADC and thus resolution
milstar: https://iopscience.iop.org/article/10.1086/677799 A 5 Giga Samples Per Second 8-Bit Analog to Digital Printed Circuit Board for Radio Astronomy
milstar: https://www.int.uni-stuttgart.de/en/research/ic/fi-adc/ . Therefore, we use various of such modern BiCMOS technologies for the design of very fast and broadband data converter front-ends with high linearity. The transistors can show transit frequencies of up to 320 GHz at the moment. Am example of such a Track-and-Hold circuit with a conversion rate of 6.4 GS/s and a nominal resolution of 9.5 bit with 2 Vpp differential input voltage range and 50 dBc dynamic range is shown in the following figure. It can be used for parallelization of data converters with lower sampling rates to vastly improve the performance e.g. of radio frequency sensors.
milstar: Photonic ADC (- in russian, Ôîòîíûå ÀÖÏ) Article (PDF Available) · February 2015 with 553 Reads Cite this publication Rostislav S. Starikov 21.39National Research Nuclear University MEPhI https://www.researchgate.net/publication/280640714_Photonic_ADC_-_in_russian_Fotonye_ACP
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