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Operazionnie ysiliteli ,ZAP/AZP & (продолжение)
milstar: 1941: First (vacuum tube) op-amp An op-amp, defined as a general-purpose, DC-coupled, high gain, inverting feedback amplifier, is first found in US Patent 2,401,779 "Summing Amplifier" filed by Karl D. Swartzel Jr. of Bell labs in 1941. This design used three vacuum tubes to achieve a gain of 90dB and operated on voltage rails of ±350V. ###################################################### It had a single inverting input rather than differential inverting and non-inverting inputs, as are common in today's op-amps. Throughout World War II, Swartzel's design proved its value by being liberally used in the M9 artillery director designed at Bell Labs. ######################################################################### This artillery director worked with the SCR584 radar system to achieve extraordinary hit rates (near 90%) that ####################################################################### would not have been possible otherwise.[3] ########################### http://en.wikipedia.org/wiki/Operational_amplifier
milstar: https://www.st.com/content/st_com/en/about/innovation---technology/BiCMOS.html 0.055 mkm SiGE Bicmos
milstar: This paper describes the design of a high-speed 8-bit Analog to digital converter (ADC) used in direct IF sampling receivers for satellite communication systems in a 0.25 μm, 190 GHz SiGe BiCMOS process. A high resolution front-end track-and-hold amplifier (THA), a low impedance reference and interpolation resistive ladder and high resolution comparators enable the ADC to achieve good performance for input frequencies of up to one-quarter of the sampling rate. The final post layout simulated system features an ENOB of 7.2-bits at an input frequency of 3.125 GHz and a sampling rate of 12.5 GS/s with a FOM of 12.9 pJ per conversion. Both DNL and INL are within 0.5 and 1 LSB, respectively Fig. 3 Folding interpolating ADC architecture https://link.springer.com/article/10.1007/s10470-009-9422-7
milstar: https://www.st.com/content/st_com/en/about/innovation---technology/BiCMOS.html 0.055 mkm SiGE Bicmos
milstar: Созданием первой российской приемопередающей базовой станции для обеспечения работы сетей формата 5G занимаются сотрудники Национального исследовательского университета «Московский институт электронной техники» (НИУ МИЭТ). Исследования ведутся по нескольким направлениям, и к настоящему моменту специалисты уже проработали технологии управления средствами связи программно-конфигурируемых сетей, получения и обработки сигналов множественного MIMO, методы сетевого взаимодействия. Как сообщили в МИЭТ, разработчики нацелены на создание технологий, сокращающих суммарные задержки при передаче и обработке пакетных данных до 1 миллисекунды и меньше. Технологии связи нового поколения 5G предполагают создание сетей с повышенной пропускной способностью, что даст возможность пользователям получать мультимедийный контент максимально быстро и в наилучшем качестве. По предварительным оценкам, создание каждой базовой станции 5G-связи обойдется примерно в три миллиона рублей. Предполагается, что испытаниями и производством станций, разработанных специалистами МИЭТ, будет заниматься Уральское производственное предприятие «Вектор». Напомним, что в соответствии с программой «Цифровая экономика», сотовая связь формата 5G появится до 2022 года в пяти крупнейших мегаполисах страны, а еще через два года сети пятого поколения должны охватить все российские города с населением более миллиона человек. Источник: www.innoros.ru
milstar: http://www.eecg.toronto.edu/~sorinv/papers/az_jssc_sept19.pdf
milstar: http://www.apissys.com/views/media_produit/datasheets/11/AF202-0.pdf
milstar: http://mil-embedded.com/articles/high-speed-drive-design-next-generation-satcom-systems/ An example of a fully digital SATCOM system designed to handle S-band signals was recently developed by a leading SATCOM provider. (Figure 1.) The system uses the Curtiss-Wright CHAMP-WB-DRFM OpenVPX module, which combines both 12 Gsps ADCs and DACs and a Xilinx Virtex-7 FPGA
milstar: https://www.spiedigitallibrary.org/conference-proceedings-of-spie/10562/105625U/High-speed-high-frequency-electro-photonic-ADC-for-space-enabled/10.1117/12.2296202.full?SSO=1
milstar: http://sss-mag.com/pdf/ad4.pdf
milstar: https://www.researchgate.net/publication/325598727_Broadband_photonic_ADC_for_microwave_photonics-based_radar_receiver
milstar: https://www.sandia.gov/radar/imagery/index.html https://www.sandia.gov/radar/video/index.html https://www.sandia.gov/radar/publications/index.html
milstar: The Interstellar H2020 Project Overview The Interstellar project is funded by the EU Commission and Teledyne e2v is leading the development of two data converters to help bridge the RF world. These are an Analog-to-Digital (ADC) converter and a Digital-to-Analog (DAC) converter. The Interstellar project is a consortium led by Teledyne e2v and supported by Thales Alenia Space, Airbus Defence and Space and the Franhofer Institute. The total budget for the project is 7.3 million Euros and the EU has contributed 6.2 million Euros of this. Teledyne e2v is investing even further into the project to drive the progresses of the data converter technology. The data converters The first device developed under the Interstellar project is a four-channel ADC named EV12AQ600. With sampling speeds up to 6 GSPs, the device offers ultra-wide input bandwidth, flexibility and high-speed serial outputs. The second device to be developed under the Interstellar project will be a multi-channel DAC, reconstructing beyond 6 GSPs it offers multi-Nyquist output bandwidth, configurable modes and high-speed serial inputs. https://www.teledyne-e2v.com/products/semiconductors/adc/ev12aq600/ The most advanced and versatile quad-core, multi-channel ADC The first 12-bit ADC to feature a Cross Point Switch (CPS), the EV12AQ600 can operate its four cores simultaneously, independently or paired, to assign its 6.4 GSps sampling speed across the user’s desired channel count: Quad-channel at 1.6 GSps Dual-channel at 3.2 GSps Single-channel at 6.4 GSps SFDR in 4 channels mode without H2 and H3 harmonics is better than 70 dBFS at -1 dBFS up to 5980MHz. https://www.teledyne-e2v.com/shared/content/resources/File/documents/broadband-data-converters/EV12AQ600/DS%2060S%20218366%20EV12AQ60x%20revA.pdf
milstar: A single-core architecture also has advantages in terms of latency. Fore examples, latencies as low as 3 clock cycles as found with the EV12AS200 ############################################# [2] are very useful in applications such as EW and tracking systems. #################################### https://www.eenewsanalog.com/content/selecting-high-speed-adcs-high-frequency-applications/page/0/2 The performance of the system can be enhanced even further using post processing and real-time techniques, such as integral nonlinearity (INL) correction and using dither to improve SFDR. The shape of the INL curve plays a large part in the harmonic performance of the ADC. By characterizing this INL and using a look-up table (LUT) in the interface FPGA, the INL can be minimized, which brings benefits for the SFDR performance. The look-up table correction is a simple subtraction or addition of the measured INL value for the code. Using this technique has very little impact on the size of the FPGA and no impact on throughput. In some cases, the addition of a LUT for INL correction can improve SFDR by 10dB. The SFDR can also be improved by adding an out-of-band noise source to the input data. This can simply be a low-pass-filtered noise generator added to the input signal using a multi-port transformer. This has the effect of moving the input signal around the input scale of the ADC, which reduces the INL effect and improves SFDR (see Figure 4).
milstar: https://pdfs.semanticscholar.org/a868/e2d948b01cef975868088cf23f1f0c2041f2.pdf photonic ADC
milstar: The narrower bandwidth ofthe digitized frequency window (i.e., 1 GHz) was characterizedwith performance of as much as 8.1, 8.0 and 7.4 ENOBs at31.51, 39.49 and 49.49 GHz, respectively. This is, to the best ofthe authors’ knowledge, a full 1 ENOB better than any reportedADC or MDC at 40 GHz and 50 GHz with 1 GHz or higherbandwidth, to date. https://www.osapublishing.org/DirectPDFAccess/9F87BF7B-F585-2B09-EC67A2BA104A493C_315527/jlt-33-11-2256.pdf?da=1&id=315527&seq=0&mobile=no In particular, the photonic assisted ADCs have been shown tobe directly applicable in microwave and millimeter wave down-conversion schemes [3]–[6]. In fact, the last down-conversionapproach has recently been implemented in field trials for afully photonics based radar [7]. In these high frequency sys-tems, carrier frequencies can typically be orders of magnitudegreater than their signal carrying bandwidth. As a result, thecarrier frequency down conversion is useful to reduce the re-quirements of the backend ADC. This, what is often referredto as conventional down-conversion, is usually achieved by alocal oscillator (LO) and a mixer that translate the signal toan intermediate frequency as depicted in Fig. 1(a). However,the reliance on a single LO implicitly assumes the knowledgeabout the exact position of the signal carrier frequency (in or-der to achieve the down-conversion to baseband), which maynot be the case in applications such as RADAR, thus in effectpreventing the detection of signals of arbitrary, or varying car-rier frequency. As a simpler alternative, the down conversioncan be performed directly by means of subsampling (at a ratelower than two times the carrier frequency), effectively takingadvantage of aliasing to down-convert the unknown microwaveor millimeter-wave frequency to the first Nyquist zone, therebyeliminating the need for exact knowledge of the signal (or theLO) position. As stated above, the conceived method is appli-cable only for signals whose bandwidth is smaller than halfof the (sub) sampling rate. The latter method can be put intopractice by means of photonic assisted ADCs that can directlydown convert a signal with high fidelity and wide bandwidthsampling, thus allowing complex digitization steps to be com-pleted in electronics at a lower rate, all the while without theneed for an LO matching the signal carrier frequency. Follow-ing their functionality, these devices are often denoted to as themicrowave-to-digital converters (MDC) [3]
milstar: In particular, the constructed photonic ADC prepro-cessor performance was rigorously characterized at a record of 7.1 (8.0) and 6.7 (7.4) ENOBs at 39.49 and 49.49 GHz,with 5 GHz (1 GHz) bandwidth, as well as with 99 dB·Hz2/3spurious-free dynamic range (SFDR) for the 30–40 GHz range,demonstrating the unprecedented highly linear, high accuracyADC/MDC. These results are compared with previous imple-mentations using a new figure of merit (FOM) for photonicsampled ADC, and they show the highest FOM value for sig-nals up to 50 GHz, to the best of the authors knowledge. https://www.osapublishing.org/DirectPDFAccess/9F87BF7B-F585-2B09-EC67A2BA104A493C_315527/jlt-33-11-2256.pdf?da=1&id=315527&seq=0&mobile=no
milstar: The high speed ADC is one of the primary design considerations in all wideband EW receivers and largely determines system architecture and overall detection and observation capability. Many performance characteristics of the high speed ADC, including sample rate, bandwidth, and resolution, are determining factors on how the rest of the receiver is designed—all the way from the analog RF domain to the DSP requirements. https://www.analog.com/en/technical-articles/28-nm-adcs-enable-next-gen-electronic-warfare-rec-sys.html# This insatiable need for higher sample rate and better resolution has led high speed ADC manufacturers to move to increasingly smaller transistor lithographic nodes (currently 28 nm and 16 nm) that enable these requirements to be achieved without increasing device power consumption. Taking the inherently lower power consumption into consideration makes ADCs on the 28 nm process key enablers in next-generation EW systems with performance and capability requirements previously considered impractical on the ≥65 nm process. The greater sample rates (several GSPS and above) achievable with 28 nm ADCs are one of the most attractive ADC features to most EW system designers, especially for SIGINT, ###################################################### electronic protect (EP), and electronic support (ES) applications. Just as important as ADC bandwidth is the resolution, which allows for greater SNR/SFDR and subsequent ability to detect, observe, and process a target signal. Undersampling beyond the 1st Nyquist is also possible as a result of higher analog input bandwidths.
milstar: https://www.analog.com/en/analog-dialogue/articles/whats-up-with-digital-downconverters-part-1.html
milstar: The TADF-4300 module supports sampling in the 2nd nyquist zone, to analyze signals up to 8 GHz and provides sub-30 ns latency for the ADC and sub 10ns for the DAC. Spurious Free Dynamic Range varies over frequency, and is >58 dB up to 3 GHz and decreases to 45 dB from 3 GHz to 6 GHz signal input frequency. ENOB varies linearly from 7.2 at low frequency, 6.5 at 3 GHz and 6.2 at 6 GHz. https://www.embedded.com/curtiss-wright-launches-high-bandwidth-high-resolution-platform-for-drfm-in-defense-and-aerospace/ https://www.curtisswrightds.com/products/cots-boards/fpga-cards/6u-fpga-processors/champ-wb.html
milstar: ad9213-10g 10gsps 4ghz 7.9 bit ENOB SFDR 60 dbfs 2.6 ghz 8.1 bit ENOB SFDR 65 dbfs
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