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Boewie wichislitel'nie kompleksi (продолжение)
milstar: http://drops.dagstuhl.de/opus/volltexte/2006/732/pdf/06141.AthanasPeter.Paper.732.pdf Although an FPGA’s clock rate rarely exceeds one-tenth that of a PC, hardware implemented digital filters can process data at ###################################################################### many times that of software implementations [4] ################################### . Additional performance gains have been described for cryptography [5], network packet filtering [6], target recognition [7] and pattern matching [8], among other ########################################################################## applications. A. Present Day Cost-Performance Comparison Owing to the prevalence of IEEE standard floating-point in a wide range of applications, several researchers have designed IEEE 754 compliant floating-point accelerator cores constructed out of the Xilinx Virtex-II Pro FPGA’s configurable logic and dedicated integer multipliers [16-18]. Dou et al published one of the highest performance benchmarks of 15.6 GFLOPS by placing 39 floating-point processing elements on a theoretical Xilinx XC2VP125 FPGA [19]. Interpolating their results for the largest production Xilinx Virtex-II Pro device, the XC2VP100, produces 12.4 GFLOPS, compared to the peak 6.4 GFLOPS achievable for a 3.2 GHz Intel Pentium processor. Assuming that the Pentium can sustain 50% of its peak, the FPGA outperforms the processor by a factor of four for matrix multiplication. One of the earlier projects demonstrated a 23x speedup on a 2-D FFT through the use of a custom 18-bit floating-point format [26]. More recent work has focused on parameterizible libraries of floating-point units that can be tailored to the task at hand [27-29]. By using a custom floating-point format sized to match the width’s of the FPGA’s internal integer multipliers, a speedup of 44 was achieved for a hydrodynamics simulation [30] using four large FPGAs. Nakasato and Hamada’s 38 GFLOPS of performance is impressive, even from a cost-performance standpoint. For the cost of their PROGRAPE-3 board, estimated at $15,000, it is likely that a 15-node processor cluster could be constructed producing 196 single precision peak GFLOPS. Even in the unlikely scenario that this cluster could sustain the same 10% of peak performance obtained by Nakasato and Hamada’s for their software implementation, the PROGRAPE-3 design would still achieve a 2x speedup. As in many FPGA to CPU comparisons, it is likely that the analysis unfairly favors the FPGA solution. Hardware implementations require specialized skills in digital design and vendor-specific tool flows. Development time and costs are significantly higher than for software. Many comparisons in literature spend significantly more time optimizing the hardware implementations than they do optimizing their software implementations. Previous research has demonstrated significant compiler inefficiency for common HPCfunctions [31]. For the DGEMM matrix multiplication function, a hand-coded version outperformed the ############################################### compiler by greater than eight times. ############################ A to- tal of 39 PEs can be integrated into the xc2vp125-7 FPGA, reaching performance of, e.g., 15.6 GFLOPS with 1600 KB local memory and 400 MB/s external memory bandwidth 1 is s 1700 nozkami i wisokoj stoimost'ju porjadka 8000 $ segodnja http://ce.et.tudelft.nl/~george/publications/Conf/FPGA05/FPGA05Dou.pd http://www.xilinx.com/publications/matrix/virtexmatrix.pd Xilinx Vertex FPGA
milstar: Курс на импортозамещение действует в России уже несколько лет. Чем этот курс помог вашей компании? Каковы итоги последних двух лет? Леонид САЛЬНИКОВ (USN Computers): Только тем, что в тендерах госзаказчиков появились требования о российском производстве ПК и серверов. Но так как клиенты из государственного сектора занимают примерно 3-4% среди всех наших клиентов, то особенного влияния на наши продажи это не оказало. https://www.it-world.ru/it-news/analytics/112503.html Игорь ЕГОРЕНКО (РАМЭК-ВС): Думаю, было бы правильнее спросить, как сильно он нам помешал. Помог он разве что китайским производителям. Тем не менее мы пытаемся жить в реалиях сегодняшнего времени и тоже взяли курс на импортозамещение. Разработали две модели ПК на процессоре «Эльбрус» и даже представили их на выставке «АРМИЯ 2016». Сейчас в планах освоение процессоров «Байкал». Кроме того, мы сертифицировали свои ПК на совместимость с ОС Astra Linux Special Edition Владимир ПИСКУНОВ («Аквариус»): Рост есть, особенно в сегменте серверов и СХД, а также локализованного ОЕМ-оборудования. В 2015 году «Аквариус» поставил свой рекорд в серверном сегменте – продано более 16 тысяч серверов. Эксперты IDC оценили весь рынок серверов в России в прошлом году чуть более чем в 100 тысяч штук. Можно ли говорить о реальной конкуренции в вопросах качества наших продуктов и иностранных? Леонид САЛЬНИКОВ (USN Computers): Можно, но, по-моему, только если речь идет о цене. Очень часто серверы HP, Dell, Lenovo даже со скидкой 50% стоят дороже, чем сервер USN Computers такой же конфигурации. Но если в компании уже есть единообразный парк какой-либо техники, то поставить туда серверы другого производителя практически невозможно. Даже по цене в два раза ниже. Думаю, вы понимаете почему. Также, на мой взгляд, сервисная поддержка у западных и восточных вендоров выстроена лучше, чем у российских, поэтому для критически важных задач многие заказчики выбирают HP, Dell, Lenovo, Huawei или других производителей.
milstar: https://www.aq.ru/products/servers/rack3U/
milstar: Xilinx FPGA 2019 Ruggedized package, fully <97% Sn on all solder points Full junction temperature support –55°C to +125°C Mil Std 883 Group D environmental characterization Mask set control Anti-counterfeit marking 475K–1143K System Logic Cells 1824–1968 DSP Slices ECC on all memories Up to 5X PCIe Gen4x8/3x16 Up to 32X GTH 16.3Gb/s and up to 24X GTY 28.2Gb/s https://www.xilinx.com/products/silicon-devices/fpga/xq-kintex-ultrascale-plus.html https://www.xilinx.com/products/silicon-devices/fpga/xq-virtex-ultrascale-plus.html Ruggedized package, fully <97% Sn on all solder points Full junction temperature support –55°C to +125°C Mil Std 883 Group D environmental characterization Mask set control Anti-counterfeit marking 862K–2835K System Logic Cells 2280–9216 DSP Slices ECC on all memories Up to 4X PCIe Gen4x8/3x16 Up to 96X GTY 28.2Gb/s
milstar: Comparing FPGA vs. Custom CMOS and the Impact on Processor Microarchitecture Henry Wong Department of Electrical and Computer Engineering University of Toronto henry@eecg.utoronto.ca Vaughn Betz Altera Corp. vbetz@altera.com Jonathan Rose Department of Electrical and Computer Engineering University of Toronto jayar@eecg.utoronto.ca https://www.researchgate.net/publication/221224729_Comparing_FPGA_vs_Custom_CMOS_and_the_impact_on_processor_microarchitecture
milstar: FPGA vs CPU vs GPU vs Microcontroller: How Do They Fit into the Processing Jigsaw Puzzle? https://www.arrow.com/en/research-and-events/articles/fpga-vs-cpu-vs-gpu-vs-microcontroller
milstar: https://www.curtisswrightds.com/products/cots-boards/processor-cards/3u-intel-dsp/champ-xd1.html#tabbed-table2 Intel Xeon D 8-Core D-1539 (410 GFLOPS @ 1.6 GHz) or 12-Core D-1559 (576 @ 1.5 GHz) April 02, 2019 News Release The combination of General Dynamics Mission Systems’ SignalEye™ software and Curtiss-Wright’s CHAMP-XD1 processor module uses machine learning to detect threats in the radio frequency spectrum. FAIRFAX, Va. – General Dynamics Mission Systems today announced its collaboration with Curtiss-Wright’s Defense Solutions division to deliver open architecture artificial intelligence (AI) based commercial off-the-shelf (COTS) solutions for signal intelligence (SIGINT) and electronic warfare (EW) situational awareness applications. “The evolving EW and SIGINT threat confronting warfighters today requires an integrated solution,” said Bill Ross, a vice president of General Dynamics Mission Systems. “By combining our SignalEye machine learning software with Curtiss-Wright’s CHAMP-XD1 processor, we can provide warfighters with a greater understanding of the RF threats on the battlefield.” The combination of General Dynamics Mission Systems’ SignalEye threat detection software and Curtiss-Wright’s Intel® Xeon® D processor-based CHAMP-XD1 module provides system designers with a deployable COTS solution for RF spectrum situational awareness that automatically classifies signals through the use of machine learning. “We are excited to collaborate with General Dynamics Mission Systems to bring the cutting-edge advantages of machine learning to deployed EW situational awareness applications,” said Lynn Bamford, Senior Vice President and General Manager, Defense Solutions division. “Our supercomputing class CHAMP-XD1 module is an ideal processor for SignalEye software, easing and accelerating the delivery of RF threat detection to our warfighters.” https://gdmissionsystems.com/articles/2019/04/general-dynamics-curtiss-wright-deliver-electronic-warfare-ai-solutions
milstar: Open-architecture electronic warfare (EW) and RF tuner mission computer introduced by Curtiss-Wright ASHBURN, Va. – The Curtiss-Wright Corp. Defense Solutions division in Ashburn, Va., is introducing the MPMC-9323/EWS Silver Palm open-architecture commercial off-the-shelf (COTS) electronic warfare (EW) and RF tuner mission computers for countering emerging battlefield threats in SIGINT, COMINT, and ELINT applications.
milstar: DSP embedded computing board for radar and electronic warfare (EW) applications introduced by Curtiss-Wright Board is for floating-point intensive DSP applications like synthetic aperture radar (SAR), sonar, multi-sensor processing, and mission computing. Oct 22nd, 2019 The board is for floating-point intensive DSP applications like specialized threat analysis and protection (STAP), synthetic aperture radar (SAR), sonar, multi-sensor processing, direction finding, and mission computing. The multi-core high performance embedded computing (HPEC) module offers advanced security features, and delivers the performance of a 12 core (576 GigaFLOPS) Intel Xeon D processor, a Xilinx Zynq UltraScale+ MPSoC (ZU4EG) FPGA, and a Flash-based Microsemi SmartFusion2 IPMC FPGA with HOST v3.0 support to deliver data security.
milstar: Planned software support for the CHAMP-XD1S includes board support packages (BSP) for CentOS 7.6 and Red Hat Enterprise Linux 7.6, and a TrustedCOTS security firmware/software package. https://www.militaryaerospace.com/computers/article/14069071/digital-signal-processor-dsp-embedded-computing-electronic-warfare-ew
milstar: JOINT BASE MCGUIRE-DIX-LAKEHURST, N.J., 27 Jan. 2013. U.S. Navy radar experts needed 6U VME single-board computers based on Freescale MPC7447A/7448 processors with AltiVec technology for radar systems aboard the littoral combat ships USS Little Rock (LCS 9) and USS Sioux City (LCS 11). They found their solution from Curtiss-Wright Controls Defense Solutions in Ottawa. Officials of the Naval Air Warfare Center Aircraft Division Lakehurst at Joint Base McGuire-Dix-Lakehurst, N.J., announced this month they plan to award a contract to Curtiss-Wright to provide 434 SVME-183 6U VME embedded computing boards for the AN/UPX 29A interrogator system and AN/UPX-24(V) interrogator sets on the Little Rock and Sioux City. Navy experts also will use the Curtiss-Wright SVME-183 computer boards for the Navy's AN/TPS-59(V)3 tactical missile defense radar, which can detect and track aircraft and missiles at ranges as far as 300 nautical miles. The value of the Navy contract to Curtiss-Wright has yet to be negotiated. The AN/TPS-59 from the Lockheed Martin Corp. Mission Systems and Training segment in Syracuse, N.Y., is a three-dimensional solid-state linear-phased array surveillance radar that operates in the D band (1215-1400 MHz), and has 54 transmitters that operate independently, and can also operate in the two-dimensional mode should its general-purpose computer fail. https://www.militaryaerospace.com/computers/article/16715347/navy-chooses-6u-vme-singleboard-computers-from-curtisswright-for-shipboard-radar
milstar: The TADF-4300 module supports sampling in the 2nd nyquist zone, to analyze signals up to 8 GHz and provides sub-30 ns latency for the ADC and sub 10ns for the DAC. Spurious Free Dynamic Range varies over frequency, and is >58 dB up to 3 GHz and decreases to 45 dB from 3 GHz to 6 GHz signal input frequency. ENOB varies linearly from 7.2 at low frequency, 6.5 at 3 GHz and 6.2 at 6 GHz. https://www.embedded.com/curtiss-wright-launches-high-bandwidth-high-resolution-platform-for-drfm-in-defense-and-aerospace/ https://www.curtisswrightds.com/products/cots-boards/fpga-cards/6u-fpga-processors/champ-wb.html
milstar: К 2020 году предприятие планирует выпуск новой ПЛИС 5578ТС064 (АЕНВ.431260.402ТУ), предназначенной для замены зарубежных микросхем EP3C55 фирмы Altera: · программируемый режим циклической перезаписи конфигурационной памяти; · встроенная система конфигурирования, обеспечивающая многократное перепрограммирование; · программируемый режим верификации конфигурационной памяти без выхода из рабочего состояния; · программируемые блоки удержания выводов пользователя в последнем состоянии; · имеется интерфейс передачи данных LVDS; · для конфигурирования ПЛИС рекомендуется использовать однократно программируемую микросхему ПЗУ 5578РТ035, ёмкостью 16 Мбит, производства АО «КТЦ «ЭЛЕКТРОНИКА»; · для проектирования используется САПР Quartus II и дополнительное ПО разработки и производства АО «КТЦ ЭЛЕКТРОНИКА»; · выпускается в 352-выводном корпусе МК 4254.352–1. · Основные характеристики ПЛИС 5578ТС084, 5578ТС094 и 5578ТС064 Характеристики https://www.soel.ru/novosti/2019/novye_rossiyskie_plis/ К 2020 году предприятие планирует выпуск новой ПЛИС 5578ТС064 (АЕНВ.431260.402ТУ), предназначенной для замены зарубежных микросхем EP3C55 фирмы Altera: Ёмкость, системных вентилей 3 000 000 Количество умножителей 18×18, шт. 156
milstar: «Ростех» представил первый суперкомпьютер на процессорах «Эльбрус» Анонсированное решение состоит из стоек, включающих 4-процессорные блейд-серверы с жидкостным охлаждением. В одной стойке могут находиться до 153 вычислительных узлов. Их суммарная вычислительная мощность составляет до 75 терафлопс двойной точности — одна стойка может выполнять до 75 трлн операций с плавающей запятой за секунду. ################################################################ Отмечается, что максимальная мощность суперкомпьютера практически не ограничена, поскольку стойки можно объединить в единый вычислительный кластер. По словам разработчиков, на охлаждение суперкомпьютера тратится менее 6 % всего потребляемого им электричества. В конструкции применены интегрированная на уровне стойки система мониторинга и специально разработанные алгоритмы управления электропитанием, повышающие энергоэффективность и отказоустойчивость оборудования. https://servernews.ru/987968?from=related-grid&from-source=993085
milstar: http://www.mcst.ru/files/5f6dde/dedece/619475/847768/katalog_elbrus_4_pokolenie_2020-2021.pdf
milstar: Эльбрус-16С продемонстрировали на выставке Микроэлектроника-2020, которая прошла в Ялте с 28 сентября по 3 октября 2020 года. На иллюстрации на фоне виден фрагмент блейд-сервера с жидкостным охлаждением на базе процессора Эльбрус-8СВ и производительностью 1,16 ТФлопс двойной точности. https://www.ixbt.com/news/2020/10/07/pervyj-vo-mnogom-v-rossii-pokazali-16jadrenyj-processor-jelbrus16s.html
milstar: http://www.ann.ece.ufl.edu/courses/eel6686_15spr/slides/Presentation1_Morales_Onishi.pdf
milstar: http://people.cs.bris.ac.uk/~simonm/publications/ClearSpeed_HPEC08.pdf
milstar: http://www.ann.ece.ufl.edu/courses/eel6686_15spr/papers/RADSPEED.pdf Applying a High Performance Tiled Rad-Hard Digital Signal Processor to Spaceborne Applications Joseph Marshall BAE Systems 9300 Wellington Road Manassas,
milstar: Tokyo, September 25, 2020 - NEC Corporation (NEC; TSE: 6701) today announced it will provide the Japan Agency for Marine-Earth Science and Technology (JAMSTEC) with a large-scale system that uses the SX-Aurora TSUBASA vector supercomputer. JAMSTEC is scheduled to begin operating the new system in March 2021 as part of the "Next Earth Simulator" project for research and development across the marine and earth sciences. Specifically, the new multi-architecture system is expected to contribute to research and development related to the global environment, marine resources, marine earthquakes and volcanic activities, as well as the creation, analysis and coordination of enormous amounts of data in a highly efficient manner. The results of these efforts are expected to help resolve policy issues and contribute to the development of a sustainable socio-economic system that capitalizes on high performance computing infrastructure (HPCI). The new system is expected to further accelerate research in the field of marine-earth science through computational resources that include a maximum theoretical performance of 19.5 petaflops (*1) ################################# centered on 684 units of SX-Aurora TSUBASA B401-8, equipped with a total of 5,472 vector engines (*2), which is approximately 15 times the performance of existing systems. Moreover, the system consumes almost the same amount of power, while requiring approximately half of the installation area. In addition, the new system makes it possible to perform more complex and larger-scale simulations at high speed, which was difficult using conventional methods. This is expected to contribute to solving global environmental issues, helping to discover causal relationships, such as that between crustal movements and earthquakes, and assisting with countermeasures against natural disasters. The SX-Aurora TSUBASA B401-8 is designed with cutting-edge technologies, including an energy-saving server technology that incorporates large numbers of card-type vector engines combining LSI technology, high-density mounting technology and high-efficiency cooling technology created by NEC over many years in the field of supercomputer development. It offers world-class single-core performance and single-core memory bandwidth, which is ideal for high speed processing of scientific calculations and large-scale data. As a result, it delivers highly sustained performance for AI and HPC applications, such as climate change projection, climate modeling, fluid analysis, nanotechnology, and the development of new materials https://www.nec.com/en/press/202009/global_20200925_01.html
milstar: The SX10+ chip is implemented in a 16 nanometer FinFET process from Taiwan Semiconductor Manufacturing Corp, which also makes Fujitsu’s and Oracle’s Sparc processors and Nvidia GPUs, among many other chips. The Aurora chip is 33 millimeters by 15 millimeters, for a die size of 494 square millimeters, which is 39.4 percent smaller than the 815 square millimeters of the Volta chip from Nvidia. This is one reason why NEC can cram more HBM2 memory onto the interposer than Nvidia can. That interposer, by the way, was designed by NEC, TSMC, and network chip maker Broadcom working together. It consumes under 300 watts at peak load, according to Momose, and we presume that means something between 275 watts and 295 watts. https://www.nextplatform.com/2017/11/22/deep-dive-necs-aurora-vector-engine/
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