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Boewie wichislitel'nie kompleksi (продолжение)
milstar: http://drops.dagstuhl.de/opus/volltexte/2006/732/pdf/06141.AthanasPeter.Paper.732.pdf Although an FPGA’s clock rate rarely exceeds one-tenth that of a PC, hardware implemented digital filters can process data at ###################################################################### many times that of software implementations [4] ################################### . Additional performance gains have been described for cryptography [5], network packet filtering [6], target recognition [7] and pattern matching [8], among other ########################################################################## applications. A. Present Day Cost-Performance Comparison Owing to the prevalence of IEEE standard floating-point in a wide range of applications, several researchers have designed IEEE 754 compliant floating-point accelerator cores constructed out of the Xilinx Virtex-II Pro FPGA’s configurable logic and dedicated integer multipliers [16-18]. Dou et al published one of the highest performance benchmarks of 15.6 GFLOPS by placing 39 floating-point processing elements on a theoretical Xilinx XC2VP125 FPGA [19]. Interpolating their results for the largest production Xilinx Virtex-II Pro device, the XC2VP100, produces 12.4 GFLOPS, compared to the peak 6.4 GFLOPS achievable for a 3.2 GHz Intel Pentium processor. Assuming that the Pentium can sustain 50% of its peak, the FPGA outperforms the processor by a factor of four for matrix multiplication. One of the earlier projects demonstrated a 23x speedup on a 2-D FFT through the use of a custom 18-bit floating-point format [26]. More recent work has focused on parameterizible libraries of floating-point units that can be tailored to the task at hand [27-29]. By using a custom floating-point format sized to match the width’s of the FPGA’s internal integer multipliers, a speedup of 44 was achieved for a hydrodynamics simulation [30] using four large FPGAs. Nakasato and Hamada’s 38 GFLOPS of performance is impressive, even from a cost-performance standpoint. For the cost of their PROGRAPE-3 board, estimated at $15,000, it is likely that a 15-node processor cluster could be constructed producing 196 single precision peak GFLOPS. Even in the unlikely scenario that this cluster could sustain the same 10% of peak performance obtained by Nakasato and Hamada’s for their software implementation, the PROGRAPE-3 design would still achieve a 2x speedup. As in many FPGA to CPU comparisons, it is likely that the analysis unfairly favors the FPGA solution. Hardware implementations require specialized skills in digital design and vendor-specific tool flows. Development time and costs are significantly higher than for software. Many comparisons in literature spend significantly more time optimizing the hardware implementations than they do optimizing their software implementations. Previous research has demonstrated significant compiler inefficiency for common HPCfunctions [31]. For the DGEMM matrix multiplication function, a hand-coded version outperformed the ############################################### compiler by greater than eight times. ############################ A to- tal of 39 PEs can be integrated into the xc2vp125-7 FPGA, reaching performance of, e.g., 15.6 GFLOPS with 1600 KB local memory and 400 MB/s external memory bandwidth 1 is s 1700 nozkami i wisokoj stoimost'ju porjadka 8000 $ segodnja http://ce.et.tudelft.nl/~george/publications/Conf/FPGA05/FPGA05Dou.pd http://www.xilinx.com/publications/matrix/virtexmatrix.pd Xilinx Vertex FPGA
milstar: rabota napisana pri podderzke Sandia National laboratory http://contentdm.lib.byu.edu/ETD/image/etd855.pdf Consider a hypothetical radar that can discriminate targets separated by more than 500 m in range. Such a system, if implemented using DSP techniques, would require a digital sampling rate of approximately 1 MHz. Ignoring a large number of details, if the system must detect targets up to 150 Km in distance, it might need to compile a 1024-point DFT every 1 milliseconds. -------- The FFT is an efficient algorithm for computing the DFT the FFT were invented prior to 1965, it was not until that year that the seminal paper by Cooley and Tukey [6] presented the first widely used FFT algorithm ----------------- Synthetic aperture radar (SAR), a type of imaging radar, operates at sampling rates of hundreds of Mega-Hertz, or even Giga-Hertz. ***************************************************** sootw ISAR ( w otlichii ot SAR RLS nepodwizna -cel podwizna ... yabch na ballist. traektorii) A 4096-point DFT might need to be computed every 800 micro-seconds. ---------------- Though the FFT offers performance advantages over the DFT, it is nevertheless an expensive operation. This is compounded by the fact that technologies continue to appear which demand ever higher data throughput, executed on larger and larger data sets. For example, some real-time radar systems require a 4096-point DFT to be computed with a data sample rate exceeding 500 million samples per second. Such a single module must execute at the equivalent rate of about 40 GFLOPS, and maintain a data throughput of 32 Gbps.
milstar: http://www.ll.mit.edu/HPEC/agendas/proc08/Day3/42-Day3-Session5-Kim-abstract.pdf
milstar: http://www.xilinx.com/support/documentation/ip_documentation/xfft_ds260.pdf
milstar: http://www.militaryaerospace.com/index/display/article-display/332820/articles/military-aerospace-electronics/volume-19/issue-6/features/special-report/radar-technology-looks-to-the-future.html Radar technology looks to the future Jun 1, 2008 Modern radar systems are combining advanced materials, solid-state modules, digital signal processors, and complex A-D converters to give a better look to military and civilian users who need the best possible capability in small, compact, and efficient packages Mark Russell, vice president of engineering for integrated defense systems at Raytheon Co. in Tewksbury, Mass ********************************************************************************************** ...In essence, once radar signals are converted from analog to digital, they are limited only by the state of the art in digital processing, which today is not a serious limitation at all. “It’s not a processing problem,” Russell says, ************************************************************************************** explaining that new powerful generations of field-programmable gate arrays are available to process complex fast Fourier transform (FFT) algorithms on which radar processing depends. ..... We can now use commercial parts for A-D converters that enable us to do direct digital sampling,” says Douglas Reep, vice president and chief engineer of the Lockheed Martin Corp. radar systems segment in Syracuse, N.Y. “We are seeing a trend where we remove analog components from systems.” “Now we can almost digitize microwave signals without the down-convert,” says Jerald Nespor, Lockheed Martin senior fellow for radar development at the company’s facility in Moorestown, N.J. Werojatno smotrja gde , tradizionno 2 preobrazowanie chastoti 35 ghz - k 1 intermedite freuency (pch) -potom k 2 IF “We need A-D converters with sufficient sampling rates to do that. na 35 ghz ? 10 bit ? .... Everyone wants higher efficiency and more dynamic range, and we can do that with COTS technologies and innovative architectures.”
milstar: “Now we can almost digitize microwave signals without the down-convert,” says Jerald Nespor, Lockheed Martin senior fellow for radar development at the company’s facility in Moorestown, N.J. Werojatno smotrja gde , tradizionno 2 preobrazowanie chastoti 35 ghz - k 1 intermedite freuency (pch) -potom k 2 IF “We need A-D converters with sufficient sampling rates to do that. na 35 ghz ? 10 bit ? .... poka oni w rajone 2 gigagerz ( 2-oj IF) *********************************************************** Stat'ja Analog Device o ADC /DAC converterax w woennix radarax i ix vlijanii na obrabotku signala http://mae.pennnet.com/display_article/366169/32/ARTCL/none/EXCON/1/Military-A/D-and-D/A-converters-come-to-grips-with-a-complex,-network-centric-world/ Military A/D and D/A converters come to grips with a complex, network centric world Analog to digital (A/D) converter and digital to analog (D/A) converter designers are struggling to keep pace with a military radio spectrum burdened with wireless PDA users, broadband Internet surfers, traditional radio communications -- and an enemy that detonates roadside bombs with cell phones and garage door openers. By John Keller Modern electronic equipment for military and aerospace applications presents systems designers with a fundamental contradiction: the real world we observe with radar systems and other RF sensor applications is analog, yet the way we process sensor information is digital. ############################ There has to be a fast, efficient, and accurate way to translate analog sensor information into digital data for efficient processing, and to translate digital data back to analog for wireless transmission and -- let's face it -- for human understanding. Enter modern analog to digital converters and digital to analog converters. These data conversion devices, designed and integrated by a handful of industry specialists, represent the crucial glue that links the analog world to the digital. Without them, much of today's high-performance digital processors would be useless in RF and electro-optical ######################################################################### applications like radar, software-defined radio, electronic warfare, missile guidance, high-end test and measurement ########################################################################### equipment, and counter improvised explosive device (IED) systems. See related story, Radiation hardened A/D and D/A converters for space electronics present special challenges. ######################################################################### Instead, systems designers would have to rely on complex and expensive analog data processors, and most likely would render information not as quickly and accurately as do today's systems that use modern A/D converters and D/A converters. With the plethora of widely available, high performance, and relatively inexpensive digital processing available today, such as multiprocessing embedded computers and field-programmable gate arrays (FPGAs), the value of the A/D converter cannot be understated. "Typically the A/D converter is selected first, and then the [digital] signal processing path behind the ADC; ##################################################################### it's one of the long poles in the tent," explains Phil Lopresti, director of the high speed data converter product at A/D converter manufacturer Intersil Corp. in Austin, Texas. ##################################### The A/D and D/A converter "really defines the overall system capability and system limits," ########################################################### adds Mike Althar, vice president and general manager of the Intersil Special Products segment in Palm Bay, Fla. As designers use the A/D and D/A converters as bridges between analog and digital data, they also must balance the amount of processing necessary for each realm. "It is always a compromise in the processing you do in the analog part of the world, and processing you do once the data becomes digital," says Andrew Reddig, president and chief technology officer at TEK Microsystems Inc., a high-performance signal processing specialist in Chelmsford, Mass. "It's easy to do lots of manipulations once you get a signal into the digital realm," Reddig explains. "Analog processing is complicated and very expensive." One goal of systems integrators is to place the A/D converter as close as possible to the sensor gathering the analog ########################################################################### signal -- typical an antenna or electro-optical sensor. ################################## In this way they can simplify their architectures and do the maximum amount of processing digitally, which is fast and inexpensive. Performance in balance A/D and D/A converters essentially have four crucial benchmarks that enable manufacturers and users to characterize their performance for different kinds of applications: 1) speed, or bandwidth, as measured in MHz or megasamples per second (the larger the number of megasamples per second, the faster the device); 2) resolution, or accuracy, as measured in bits (the larger the number of bits, the higher the resolution of the device); 3) noise and distortion rejection, as measured in decibels, or dB (the higher the decibel level, the better the device rejects noise and distortion); and 4) size, weight, and power consumption. The speed of the A/D and D/A converter describes how many signal samples per second the device can process. Typically this is measured in MHz, or millions samples per second. Some devices can take only hundreds of samples per second, and some of today's fastest devices can take 3 billion samples per second (gigasamples). ################################################################ The resolution of A/D and D/A converters refers to the detail and depth of each sample taken, and is measured in bits. The higher the number of bits, the more detailed is each sample taken. High resolution is particularly important in applications like imaging radar that must discern small objects close by ######################################################################### large objects, or in signals intelligence that must be able to characterize even the faintest radio signals in the presence of many other signals and electronic noise. ############################ Noise and distortion rejection is measured in two ways. The first is spurious noise dynamic range (SNDR), and the second is signal to noise ratio (SNR), both of which are measured in decibels, or dB. The higher the dB level of these two measurements, the better the A/D or D/A is at detecting and characterizing weak signals that may be important. Strong noise and distortion rejection is particularly important for applications like signals intelligence, radio communications, or sophisticated radar jammers. Some A/D and D/A makers will list a device's "useful bits" rating for resolution, which considers not only the part's resolution, but also its noise and distortion rejection ability. An A/D or D/A may have a high bit resolution rating, but #################################################################### poor noise rejection, which effectively would reduce its useful resolution bits rating. #################################################### Size, weight, and power consumption -- collectively referred to as SWAP -- are particularly important for portable and hand-held applications like hand-held software-defined radios and portable spectrum analyzer gear for deployed electronic warfare and IED detection, as well as for fighter aircraft, unmanned vehicles, and missile applications. Different devices, different applications Relatively large ground-based or shipboard radar applications, for example, do not depend so much on SWAP because they have ample power supplies and space. Conservative power consumption can be a factor in these kinds of applications, however, to reduce heat and the need for exotic electronics cooling schemes. "If it is part of a ship or vehicle, there are relatively few power constraints," ################################################## explains Chuck Sanna, product marketing engineer for A/D and D/A converter manufacturer Texas Instruments Inc. (TI) in Dallas. "With portable devices, the battery is the issue." The larger the application, the more the designer concentrates on pure A/D and D/A converter performance, rather ########################################################################### than on device size and power consumption says Pam Aparo, ######################################### marketing manager for device maker Analog Devices High-Speed ADC Products segment in Greensboro, N.C. "Most of the requirements we get break down into 'the sky's the limit' in the performance and power that our users need," she says. "A ground-based radar is not concerned about power; they want all the performance they can get. ####################################################################### With missiles and communications and things people have to carry, it has to be a lightweight system, so we have to get the size and power down." ##################### Something else systems integrators must consider when looking at A/D and D/A converters is the analog circuitry in the processing chain immediately before the converter. If these components are of marginal quality, it might not make sense to use a top-of the line signal converter. "It's not just the ADC that you have to think about in terms of a system," explains Duncan Bosworth, director of engineering at TEK Micro. "There are still the analog components that go into the front of it. ADCs aren't fast enough yet to see everything, so you still need to think of the ADC along with the receiver you use with it. There's no sense to have an ADC with deep resolution if your amplifier and receiver have very poor noise performance. The analog part will dominate overall performance. "A/D is the boundary between analog and digital, but it is very important to match the tuner and amplifier stage with the A/D state so that everything works together as a system," Bosworth says. TI's Sanna says A/D and D/A converter makers must consider three potential system bottlenecks: how good is the ########################################################################## analog front end that interfaces with the antenna; the digital processing behind the A/D and D/A converters; and the ########################################################################## converters themselves, which occasionally can introduce noise, distortion, or other unwanted artifacts to signals of interest. ##################### Design tradeoffs No A/D or D/A converter -- at least not yet -- can be all things to all people. One rule of thumb is the faster the ######################################################################### device, the lower its resolution and noise rejection. On the other hand, the devices with the finest resolution and noise ########################################################################## rejection typically are not the fastest devices. It all depends on the application and the designer's needs. ###################################################################### One kind of radar jammer, for example, might have a high priority on speed, at the expense of resolution. ###################################################################### Above all, this system may need to detect radar signals quickly so it wastes no time in overwhelming the enemy ########################################################################### signal with jamming energy. In this application, it is not so important to characterize the radar signal with fine ####################################################################### resolution as it is to detect the radar signal quickly and jam it. ######################################## Signals intelligence and radio communications, on the other hand, put a priority on high resolution to detect and ########################################################################## classify weak signals of interest -- particularly when the desired signals are alongside strong signals or strong sources of noise. ######## Airport security screening systems also put a priority on signal conversion resolution over speed. These X-ray systems and gas sniffers "are detecting everything from explosives and contaminants, and the higher-precision converters help with the swabbing and puffers," says Intersil's Althar. "Better resolution gets you to lower parts-per-million levels." In noise and distortion rejection, designers sometimes would like to choose between optimizing for SFDR or SNR. A/D and D/A specialist Analog Devices Inc. in Norwood, Mass., offers the AD 9268 A/D converter that has a dither switch to enable users to choose between optimizing for SFDR and SNR. "It lets the users decide if they want low noise or better spurious performance," says Analog Devices's Aparo. State of the art Users of the devices constantly push the manufacturers to improve all aspects of A/D and D/A converters. "Customers want everything -- more speed, more resolution, lower power consumption, and smaller size," says TI's Sanna. "As the military really gears up the communications network side, the main driver is increased need for lower power. A cell phone on steroids type of system drives a lot of it across the board, and the digital battlefield is a huge driver." A/D converter Nirvana for systems integrators has not materialized yet, but manufacturers are edging ever closer to ########################################################################## what might be considered the perfect device. "We asked one of our customers recently what they want in a perfect ######################################################################### world," says TEK Micro's Reddig. "They said take all of the RF [device speed] up to 18 GHz and digitize with enough ########################################################################## bits so that everything is digital, and you don't need a tuner or processing at the analog end. A/Ds don't do that yet." ########################################################################## Still, much progress is being made. Historically, at a given resolution, A/D and D/A converter designers have been able effectively to double the sampling rate of their devices without hurting SNR or SFDR every one to three years, ######################################################################### says TI's Sanna. "You can do a lot if you throw power at it," he says. So what is the state of the art in today's A/D converters? ###################################### It all depends on the device's optimization for speed or resolution. At Texas Instruments, for example, the highest-resolution device -- at 16 bits -- tops out in speed at 200 ##################################################################### megasamples per second, Sanna says. The company's best 14-bit device runs at 400 megasamples per second, and the 12-bit device runs at 550 megasamples per second. There are also 10-bit devices on the market that run at 2 ########################################################################## gigasamples per second, as well as 8-bit A/D converters running at a dizzying 3 gigasamples per second, and even ########################################################################### faster. ####### At Intersil, the state of the art is in the realm of 12 bits of resolution at a speed of 250 to 500 megasamples per ######################################################################### second. The company's best 14-bit A/D converter runs at 250 megasamples per second. Intersil's flagship product -- the KAD 5512 P-50, is a 12-bit A/D converter running at 500 megasamples per second, with signal to noise ratio of 66 ############################################################################ dB and an SFDR or 85 db. Users can push this device to speeds of 1.3 GHz, says Intersil's Lopresti. ################################################################ At Analog Devices, the best is yet to come, with anticipated new A/D converter introductions in January and April 2010. These devices will have resolutions in excess of 14 bits, speeds faster than 150 megasamples per second, and ########################################################################### optimized for SFDR, which should be in the mid-90s dB, Aparo says. ############################################# "The big leap in both of those products will be much higher linearity at wider sample rates than we have available today," Aparo says. "They will have much better spurious dynamic range, and will be for use in applications like a radar system to make sure you are not seeing false targets, and to see small targets next to large targets. In communications it helps avoid interference from other channels." Design trends One of the most noticeable design trends in A/D and D/A converters is reducing size, weight, and power consumption for applications like handheld radios and sensor packages on unmanned aerial vehicles. "We are seeing radical improvements in power consumption," says Intersil's Lopresti. "People are trying to move that kind of data acquisition technology into mobile devices, handhelds, trucks, and movable equipment." Among the approaches manufacturers are using to shrink A/D and D/A converter geometries is to increase their use of on-board digital processing to enhance functionality, reduce device size, and cut power consumption. "Smaller geometries help with power significantly," says Analog Devices's Aparo. "We use more digital processing on the device so as not to make it hopelessly large." Designers also are fabricating chips with several A/D or D/A converters on board. "Now our A/D converters are in the 12-bit resolution, and are moving into duals, quads, and potentially octals in channels on the same chip," says #################################################################### Intersil's Lopresti. "In the past you bought one 12-bit ADC, and now you can buy four to eight on the same chip." One way manufacturers seek to reduce size, cut power consumption, and increase performance is through a controversial approach called interleaving. This enables devices to work together to speed signal sampling -- much the same way that multiprocessing computers use several microprocessors working together to increase computational speed. A/D converter manufacturers like National Semiconductor in Santa Clara, Calif., Intersil, and others are pursuing interleaving technology, while others around the industry do not give this design approach much credence. ###################################################################### "People have tried ganging A/Ds together," says Rodger Hosking, vice president of signals intelligence and software defined radio processing specialist Pentek Inc. in Upper Saddle River, N.J. "In practice it is very difficult, and almost never works very well." Nevertheless, Intersil's Lopresti says A/D converter interleaving is an important part of his company's strategy. "We do, in fact, have IP that allows us to interleave these converters together, and that is how we create very-high-performance, lower-power ADCs -- by interleaving two ADCs on the same chip." It's not easy however, yet the rewards can be great. "The only real tradeoffs you have to contend with are you must have a very area-efficient core," Lopresti says. "You will probably need to use bipolar or BiCMOS to do that. The device must be very area efficient, and you have to embed some kind of digital logic to identify the interleave spurs, and then identify the corrections needed in an algorithm to eliminate those spurs." Future applications drivers The landscape for A/D and D/A converter manufacturers isn't getting any easier. Not only are systems integrators always asking for more capability, but the environment in which these devices must operate also is becoming more complex and difficult. One of the most pressing issues is crowding in the RF spectrum. The recent federally mandated digitization of commercial over-the-air television signals has opened many frequencies to new users, such as cell phone operators, wireless networking, and more. "In signals intelligence they are being inundated from signals from everywhere -- laptops on Wi-Fi network hot spots, ########################################################################### an explosion in cell phone technology with video, text, Internet surfing, and e-mail browsing," says Pentek's #################################################################### Hosking. "And in a war you have people setting off explosives with cell phones, and you have traditional battlefield communications that need to maintained, secured, and fault tolerant. This leads to higher demands of signal-to-noise performance so you can get the job done better than before." Providers of analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) Analog Devices Inc. Norwood, Mass. -----------------------------------------------------------------------------------.. Radiation hardened A/D and D/A converters for space electronics present special challenges By John Keller Analo device GREENSBORO, N.C., 16 July 2009. Suppliers of radiation hardened analog to digital converters and digital to analog converters for space electronics applications face a more difficult set of design challenges than do suppliers of A/D and D/A converters for commercial applications. "We have constraints such as traceability, radiation performance, and a long list of items," says Bob Barfield, business development manager for the Analog Devices Inc. space products segment in Greensboro N.C. Barfield says he is seeing an increase in mil spec kinds of requirements for rad hard electronic components intended for space applications -- particularly A/D and D/A converters. "From a U.S. defense space market perspective, we are seeing more and more contract flow-down requirements requiring QML V or QML R space parts," he says. The space market requires traceability and process control. A/D and D/A converter providers (see related story Military A/D and D/A converters come to grips with a complex, network centric world) for space applications are particularly concerned with what they call low radiation dose performance -- or the amount of space radiation that their components must endure over time. "Right now we are looking at 10 millirads per second," Barfield says. "Over time there are a lot of industry experts who determine that at lower dose rates we can see performance degradations not observable at higher dose rates." One of the problems of designing electronic components for space applications is the physical changes these components undergo over time while operating in space. "It's sometimes not enough to characterize a certain wafer lot, and five years down the road to expect they are still at the same performance level," Barfield says. "It is really, really process-dependent how vulnerable the ADCs are to radiation," Barfield continues." SOI [silicon-on-insulator technology] is tolerant of SEU [radiation-induced single-event upsets] and ionizing dose. If we move to more digital-type processes like CMOS, there is increased susceptibility to single-event effects. We need to be relatively careful in our characterization of parts." http://mae.pennnet.com/display_article/366353/32/ARTCL/none/EXECW/1/Radiation-hardened-A/D-and-D/A-converters-for-space-electronics-present-special-challenges/
milstar: experimentalnie ,no net razreschajuschej sposobnosti 10-12 bit kak na 2 ghz A 20 GS/s 5-Bit SiGe BiCMOS Dual-Nyquist Flash ADC With Sampling Capability up to 35 GS/s Featuring Offset Corrected Exclusive-Or Comparators ############################################################################################## Daniel, E.S. Daun-Lindberg, M.A. Schwab, D.J. Kertis, R.A. Philpott, R.A. Humble, J.S. Fritz, K.E. Prairie, J.F. Gilbert, B.K. Dept. of Physiol. & Biomed. Eng., Mayo Clinic, Rochester, MN, USA; This paper appears in: Solid-State Circuits, IEEE Journal of Publication Date: Sept. 2009 ####################################### Volume: 44, Issue: 9 On page(s): 2295-2311 ISSN: 0018-9200 INSPEC Accession Number: 10846938 Digital Object Identifier: 10.1109/JSSC.2009.2022672 Current Version Published: 2009-08-28 Abstract The design and wafer probe test results of a 5-bit SiGe flash ADC are presented. The integrated circuit, fabricated in a 200/250 GHz fT/Fmax, SiGe ############################################################################################### BiCMOS technology, provides a 5-bit analog to digital conversion with dual Nyquist operation at sample frequencies up to 20 GHz. Sampling clock rates are demonstrated as high as 35 GS/s. The ADC makes use of a comparator with an integrated exclusive-or function to reduce power consumption. The device also generates two half-rate interleaved outputs to ease data capture with laboratory equipment. An effective number of bits (ENOB) of nearly 5.0 is achieved for low-frequency input tones, dropping to 4.0 at 10 GHz. http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?tp=&arnumber=5226705&isnumber=5226685
milstar: realnie ,wesma ydalennie ot zelaemix dlja slsuchaj " bez down converting" ADS5400 Status: ACTIVE 12-bit, 1000 MSPS ADC with analog input buffer http://focus.ti.com/docs/prod/folders/print/ads5400.html
milstar: http://www.mc.com/solutions/customer-examples.aspx Quad-Channel ELINT Wideband Microwave Processor Deployed Solution (PDF) (registration required) This deployed solution lets ELINT applications for voice, data or radar monitor a wide portion of the electromagnetic spectrum for direction-finding and/or beamforming with high throughput and very low latency. Components: Echotek™ Series RF 1800GT Wideband Microwave Tuner PowerStream® 6100 RapidIO VXS Switch Card PowerStream 6100 HCD Quad PowerPC VXS Module Echotek Series ECV4-4-R1500-VXS ADC VPA-200 VXS SBC + PMC Carrier http://www.mc.com/solutions/deployed-solutions.aspx
milstar: lutschie resultati 12 bit 3.6 gigasamples National Semiconductor i 16 -bit 250 megasamples Analog Device ================================= http://www.national.com/ds/DC/ADC12D1800.pdf The 12-bit, 3.6 GSPS ADC12D1800 is the latest advance in National's Ultra-High-Speed ADC family Na 1448 megagerz 8 bit ENOB- Effective Number of Bits DES mode ,8.4 bit non DES mode `````````````````````````````````````````````````````````````````````````````` http://www.analog.com/static/imported-files/data_sheets/AD9467.pdf 16-Bit, 200 MSPS/250 MSPS Analog-to-Digital Converter Preliminary Technical Data AD9467 na 300 megaherz 12 bit ENOB- Effective Number of Bits
milstar: Analog–to–Digital Converter Technology and Corresponding Signal Processor Throughput and Dynamic Range. For the PATRIOT radar, advanced signal process technology is required to support dynamic ranges while maintaining the throughput, size, weight, and prime power requirements. Applicable advanced signal processing techniques, such as maximum entropy method (MEM), are required for incorporation into PATRIOT, along with a concept for their utilization, signal processor hardware concepts, and an assessment of their performance improvement over pulse Doppler for various environments. The PAC–3 radar signal processors currently use 12–bit A/D converters for narrow band actions. For radar performance in clutter, more dynamic range is needed—up to 14–16 bits for wide band. system/transmitter intermediate ################################################################################### frequency (S/T–IF) receiver subsystem changes would require the incorporation of 16 bit A/D converters into the PATRIOT S/T–IF receive subsystem, along with the incorporation of the advanced signal processor hardware and processor resident software. ################################################################################# Included in the proposed architecture and design is the removal or disabling of the current digital signal processor and the replacement of their functions in the advanced signal processor. The CDI–3 receiver subsystem was designed for later incorporation of 12 bit A/D converters when available. The incorporation of the 14–bit converter will require some redesign of the receiver. The value added for PATRIOT is improved fire unit search, track, and CDI capabilities in low altitude, high clutter or extensive antitactical missile debris environments. The technology infusion period is from 1QFY02 to 4QFY03. [POC: Rodney Sams, PATRIOT, (205) 955–3166] http://www.fas.org/man/dod-101/army/docs/astmp98/de.htm
milstar: Mercury Computer Systems is Selected by Northrop Grumman to Deliver Radar Processing for Persistent Maritime ISR in U.S. Navy BAMS Program 4 months 1 week ago → Contracts (click image to zoom by 2.2x) CHELMSFORD, Mass. - June 17, 2010 - Mercury Computer Systems, Inc. (NASDAQ: MRCY), a trusted ISR subsystems provider, announced it was selected by Northrop Grumman Corporation (NYSE: NOC) to deliver its scalable multicomputing products and services for the U.S. Navy Broad Area Maritime Surveillance (BAMS) Program. Mercury will provide PowerStream® 7000 multicomputers*, the most powerful embedded computing platform in deployment, and a heterogeneous operating system for the BAMS UAS to enable the processing of synthetic aperture radar (SAR) images. The BAMS UAS is designed to support a variety of all-weather maritime ISR (intelligence, surveillance and reconnaissance) missions. “We’re pleased to work with Northrop Grumman to provide persistent maritime ISR capability to warfighters,” said Brian Hoerl, Vice President of Worldwide Sales at Mercury. “Mercury’s PowerStream multicomputers, which are deployed on some of the world’s largest radar platforms, combine the power of FPGA processors with massive I/O and real-time reconfiguration, delivering the performance density and reliability necessary for this vitally important application.” For more information on Mercury’s multicomputing solutions, visit www.mc.com/products/systems/powerstream7000.asp[...], or contact Mercury at (866) 627-6951 or at info@mc.com. http://www.mil-embedded.com/news/db/?22501#__utma=1.509730357.1288007371.1288007371.1288007371.1&__utmb=1.1.10.1288007371&__utmc=1&__utmx=-&__utmz=1.1288007371.1.1.utmcsr=search|utmccn=%28organic%29|utmcmd=organic|utmctr=atmel%20ADC%20military%20radar&__utmv=-&__utmk=175406754 http://www.mc.com/products/systems/powerstream7000.aspx Features * High-density computing with over 1 TFLOPS peak performance * RapidIO®-based communications with 60 GB/s bisection and 75 GB/s aggregate bandwidth * 16 GB/s streaming fiber I/O using serial FPDP * FreescaleTM MPC7447A PowerPC® microprocessors with AltiVecTM technology * Performance density exceeding 150 GFLOPS per cubic foot * Patented air-cooling system with ManagedAir™ technology * 32 Mezzanine sites for PMC and XMC modules * 16 GB ethernet interfaces http://www.mc.com/products/systems/powerstream7000.aspx
milstar: http://www.vigstar.ru/russian/grt.pdf Bortowaja obrabotka signala (na sputnike)
milstar: Radiation-hardened SPARC processor for space missions EDN Europe, 28 Jul 2009 Atmel has introduced a radiation-hardened SPARC processor for space applications, http://www.edn-europe.com/radiationhardenedsparcprocessorforspacemissions+article+3267+Europe.html
milstar: http://www.edn-europe.com/radiationhardenedsparcprocessorforspacemissions+article+3267+Europe.html Radiation-hardened SPARC processor for space missions EDN Europe, 28 Jul 2009 Atmel has introduced a radiation-hardened SPARC processor for space applications, the AT697 Revision F, delivering 90MIPS at 100MHz over full temperature and voltage ranges for 0.7W. This SPARC V7 processor version includes more than 1600 flight models of its predecessor, the TSC695E. The AT697 Revision E was the first version of a SPARC V8 processor and has a computing power efficiency of 90MIPs. The radiation performance of the AT697 Revision F include: total dose tested up to 300Krad; reliable against single event upset and transient (SEU and SET induced error rate better than 10-5 errors/device/day); and no single event latch-up below a LET threshold of 95MeV.cm²/mg at +125°C. The design is based on the ESA (European Space Agency) LEON2-FT (Fault Tolerant) model and includes the new techniques of radiation hardening by design including full triple modular redundancy, EDAC and parity bit protections. With its 90MIPs (Dhrystone 2.1) and 23MFlops (Whetstone) high performance, the AT697F offers computing power efficiency of 150MIPS/W. The AT697F is software compatible with the other Atmel space SPARC processors. Related Articles (Latest) 1. ARM MPU features integrated Profibus interface 6/12/2010 2. Handheld spectrum analysers facilitate installation of CDMA and LTE networks 30/11/2010 3. Two-channel single-chip IO-Link for master applications 30/11/2010 4. Development tool support for MPUs helps minimise project risks 30/11/2010 5. New multicore DSPs posses enhanced fixed- and floating-point capabilities 11/11/2010 Free Print Subscription Printer-friendly versionEmail to a Friend http://www.edn-europe.com/radiationhardenedsparcprocessorforspacemissions+article+3267+Europe.html
milstar: Эльбрус-8С 27.06.2014, 10:17 Новостная служба Ferra, news@ferra.ru Версия для печати Российская компания МЦСТ объявила о запуске в производство опытной партии универсальных микропроцессоров Эльбрус-8С. Расчётная рабочая частота чипа - 1,3 ГГц, технология производства – 28 нм, вычислительная мощность составляет 250 гигафлопс. Получение готовых образцов микросхем ожидается в октябре 2014 года. http://www.ferra.ru/ru/techlife/news/2014/06/27/elbrus-8C-start/#.VH8l9IsahW8
milstar: Слово за отечественной микроэлектроникой Версия для печати Добавить в избранное Обсудить на форуме Новый путь создания вычислительных комплексов для оборонных объектов может стать в 15 раз дешевле Ярослав Хетагуров Тэги: технологии, микроэлектроника, опк, компьютеры Создаваемые сегодня вычислительные средства управляющих систем оборонного значения, работающие на отечественных элементах, не позволяют значительно увеличивать быстродействие, объем памяти и достоверность выдаваемой информации без существенного увеличения габаритно-массовых показателей и потребления электропитания. Использование же для решения задач военного назначения иностранных микропроцессорных средств таит в себе большие проблемы, связанные с безопасностью и защищенностью, а также с экономией при длительной эксплуатации. Необходимо отметить, что применение вычислительных средств и программного обеспечения иностранного производства практически дает возможность получения любой закрытой информации иностранным службам, то есть не обеспечивает безопасность и защищенность. Президент и премьер-министр России отметили в своих выступлениях необходимость решения этой задачи. Иностранные государства – США, Англия, Франция и ФРГ для безопасности и защищенности своих систем перешли к использованию микропроцессоров, контроллеров и других элементов собственного производства и систем программного обеспечения собственной разработки. Только при этих условиях обеспечивается независимость работы систем от многих внешних и внутренних факторов. В настоящее время рассматривается комплексная задача создания вычислительных средств оборонного назначения, работающих на отечественной элементной базе и решающих задачи безопасности, защищенности, экономичности и длительной – порядка 10–20 лет – эксплуатации. Это становится возможным на основе нового метода построения вычислительных устройств с применением инновационного принципа кодирования величин. Инновационный принцип построения основан на новом способе кодирования информации «1 из 4», в котором из четырех состояний кода используется только одно. Предлагаемый метод позволяет обеспечить контроль работы вычислительного устройства, а также сократить: объем аппаратуры – в 1,5 раза по отношению к мажоритарному методу контроля, время выполнения операции – в 2–3 раза, потребление электроэнергии – в 5 раз. Для контроля и восстановления испорченной информации сокращаются затраты времени более чем в 3 раза и объема аппаратуры в 4 раза. Использование освоенной нашей промышленностью технологии создания базовых кристаллов БИС решает проблему промышленного производства инновационных вычислительных устройств и систем обмена информации в коде «1 из 4». При этом сокращается время создания БИС до 4–5 месяцев, а затраты на производство снижаются в 10 и более раз. Создание оборонных комплексов вычислительных систем на инновационном принципе кодирования «1 из 4» сокращает количество команд программы решения задач по сравнению с применением двоичного кодирования в среднем в 15 раз, за счет исключения проверяющих программ, обеспечивает защищенность и безопасность, гарантируемую построением систем на отечественной аппаратурной базе, минимизирует затраты на создание и эксплуатацию вычислительных комплексов. Ярослав Афанасьевич Хетагуров – доктор технических наук, профессор, академик Международной академии информации (МАИ), главный конструктор корабельных цифровых вычислительных систем (КЦВС) стратегических ракетных комплексов подводных лодок. http://nvo.ng.ru/concepts/2014-12-26/7_micro.html
milstar: омпания МЦСТ запустила в производство опытную партию микропроцессоров «Эльбрус-8С» с технологией производства 28 нм, расчетной рабочей частотой чипа 1,3 ГГц и вычислительной мощностью 250 Гфлопс. Получение готовых образцов микросхем ожидается в октябре текущего года. А создание инженерных образцов 4-процессорного сервера на базе «Эльбрус-8С» с производительностью 1 Тфлопс намечено на конец 2014 г. Как уточнили s в МЦСТ, микросхемы и серверы, готовые к серийному производству, должны появиться в 2015 г. Изначально серверное решение будет спроектировано и создано силами МЦСТ, а дальше компания станет рассматривать предложения по выпуску продукции сторонними подрядчиками. В настоящий момент известно, что сервер будет размещен в 19-дюймовой стандартной стойке, и по предварительным оптимистичным прогнозам решение будет потреблять порядка 60 Вт на процессор (реальное потребление может оказаться выше). В базовой конфигурации сервер будет иметь до 6 портов Gigabit Ethernet, 2 порта PCI-Express 2.0 x16 и 2 порта PCI-Express 2.0 х4 и до 16 портов Serial ATA 3.0. Возможности расширения включат в себя дополнительные 4 порта Gigabit Ethernet и дополнительные 16 портов SATA 3.0. В МЦСТ обращают внимание на то, что "Эльбрус-8С" — это полностью российская разработка. Кристалл микропроцессора имеет 8 ядер с 64-разрядной архитектурой "Эльбруса" 3-го поколения, кэш-память 2-го уровня общим объемом 4 мегабайта и 3-го уровня объемом 16 МБ. На базе микропроцессора Эльбрус-8С планируется организовать массовое производство серверов, рабочих станций и других средств вычислительной техники, предназначенных для применения в госучреждениях и бизнес-структурах, предъявляющих повышенные требования к информационной безопасности, а также для применения в области высокопроизводительных вычислений, обработки сигналов, телекоммуникации. В МЦСТ обращают внимание на то, что разработанная в России архитектура «Эльбрус» имеет ряд исключительных особенностей. К ним в компании относят возможность выполнять на каждом ядре до 25 операций за один машинный такт (что обеспечивает высокую производительность при умеренной тактовой частоте), технологию динамической двоичной трансляции (что обеспечивает эффективное исполнение приложений и ОС, распространяемых в двоичных кодах x86, в том числе в многопоточном режиме), поддержку режима защищенных вычислений с особым аппаратным контролем целостности структуры памяти (что позволяет обеспечить высокий уровень информационной безопасности использующих его программных систем). Базовой операционной системой для платформы «Эльбрус» является одноименная ОС, построенная на базе ядра Linux. Система программирования платформы поддерживает языки С, С++, Java, Фортран-77, Фортран-90. При этом стоит отметить, что в апреле 2013 г. директор компании МЦСТ и Института электронных управляющих машин, где базируется МЦСТ, Александр Ким рассказывал, что, имея перспективную архитектуру и уникальные технологии, компания, тем не менее, не может довести их до продуктового состояния и продвинуть на рынок, поскольку не имеет достаточных финансовых ресурсов. Предыдущее значимое объявление МЦСТ сделал в конце апреля текущего года, когда сообщил о готовности к серийному производству отечественного процессора нового поколения «Эльбрус-4С». Отметим, что в 2014 г. после некоторого перерыва продолжилось сотрудничество МЦСТ с Минпромторгом. В марте текущего года компания выиграла тендер на разработку универсального 8-ядерного 64-разрядного микропроцессора с пиковой производительностью 512 Гфлопс до ноября 2018 г. на сумму в 620,95 млн. руб. Финансирование предусматривает выделение 7,75 млн в 2014 г., 40 млн в 2015 г., 188,2 млн в 2016 г.; объем средств на 2017-2018 гг. будет определен позже. Что касается «Эльбрус 8С», то работы над ним ведутся в рамках контракта заключенного еще в конце 2011 г. Изначально его предметом являлись «интеллектуальная и материальная продукция, услуги по исследованиям и разработкам, нефинансовые нематериальные активы в области естественных и технических наук». Его цена составляла i760 млн, выделяемых неравными долями до 2015 г. Однако с февраля 2012 г. по февраль 2013 г. контракт был трижды изменен, и в настоящий момент его предметом прописана «разработка гетерогенного микропроцессора с пиковой производительностью более 150 Гфлопс на базе высокопроизводительных универсальных 64-разрядных процессорных ядер». Новая цена — i836 млн. В текущем году финансирование проекта составит i246,25 млн, а в следующем (завершающем) — i167,8 млн.
milstar: The Wasp CF-19 is the kind of laptop to accompany you on the construction site, surveying job, research expedition or field maneuver. It has been independently tested as MIL-STD-810F (U.S. military standard) compliant, meaning it can withstand punishment such as: a fall of 1 meter, 15,000 feet of altitude and an operating temperature range of -20 to 140 degrees Fahrenheit. Other tests include vibration (drives are shock-mounted), dust, humidity, water resistance, thermal shock, etc.. Given its rugged exterior, the Wasp CF-19 is quite light at 5 lbs. with its magnesium alloy casing. Other features are a shielded yet very daylight-readable 10.4" XGA display (1024 x 768), recessed and snugly capped ports, a tablet-based display with handwriting recognition, a tough swivel and a strong metal clasp that can secure the lid closed or in tablet-up position. The latchable compartment containing the Wi-Fi on/off switch, PC card slot, express card slot, SD reader is another smart addition. Our test machine was configured as follows: Fedora Linux 7 + Windows XP dual boot, 1.067 GHz Intel Core Duo U2400 ultra-low voltage processor, 1.5 GB of RAM, 80 GB hard drive, and no optical drive (an external USB DVD/CD-RW costs an extra $400). EmperorLinux is absolutely fanatical about offering a rich Linux-based experience, and the Wasp CF-19 lets them put their expertise on display. In addition to the expected features like Fn-keys all working, the Wasp CF-19 has a number of optional features atypical for Linux laptops, such as the tablet functionality with screen rotation and mobile broadband (EV-DO or HSPDA) and internal GPS support. And Emperor makes them work out of the box. The custom documentation is also excellent, explaining what does work (and how) and what does not work, saving the user precious time and headaches. If only Emperor would add a custom menu like R Cubed, another Linux laptop vendor, which offers custom installation of applications, system and kernel updates and direct support options, they'd have the best of all worlds. http://www.linuxjournal.com/node/1000431 http://www.emperorlinux.com/mfgr/panasonic/wasp/
milstar: Panasonic CF-19 Linux Debian Наконец-то! УРА! Спасибо большое! Заработала беспроводная сеть на Panasonic CF-19. А теперь что со звуком делать? И экраном сенсорным...? Ура! Наконец-то сбылось и Debian заработал идеально! Спасибо Вам огромное! Скрипт экрана работает на ура. http://linuxmd.net/forum/debian/203-resheno-panasonic-cf-19-problemy?start=20
milstar: Applying a High Performance Tiled Rad-Hard Digital Signal Processor to Spaceborne Applications BAE http://www.ann.ece.ufl.edu/courses/eel6686_15spr/papers/RADSPEED.pdf On-board processing may be performed in a variety of ways including 1) specialized radiation hardened application specific integrated circuits (ASIC) with their highest performance/watt but limited functional flexibility, 2) reprogrammable field programmable gate arrays (FPGA) with higher power requirements and additional challenges in radiation mitigation and configuration storage; 3) multi-core general purpose processors (GPP) with floating point units supported by COTS infrastructure but with lower overall performance and 4) multi-core digital signal processors (DSP) optimized for signal processing applications that provide programmability and high performance at a reasonable power. The RADSPEEDTM DSP - a radiation hardened version of the ClearSpeedTM CSX700 digital signal processor – is being developed by BAE Systems to provide a high performance per watt digital signal processor for these emerging spacecraft applications. The CSX700 is a best in class device in the commercial world and is used in a variety of graphics, financial, server and other signal processing applications supported by a full set of development tools. In hardening the RADSPEED DSP, over 70% of the performance of the commercial device was retained (70 GFLOPS peak performance) with a modest decrease in processing speed (8%) and the number of processing element cores (160 from 200). The RADSPEED DSP opens up a programmable world for specialized payload applications. This includes 1) various types of RF processing, 2) radar processing with the high throughput required for both Space-Time Adaptive Processing (STAP) and Synthetic Aperture Radar (SAR) algorithms, 3) hyperspectral imaging with the need for simultaneous processing of images across a number of frequency bands, fusing data for analysis, spectral analysis for the simultaneous assessment of data across a number of frequency bands and 4) image processing including edge and object detections and the efficient distribution of a high resolution image across a series of parallel processing elements. . RADSPEED DSP DEVELOPMENT The RADSPEED DSP is a variant of the ClearSpeedTM CSX700 [5] DSP. BAE Systems and ClearSpeed Technology modified the device for the space environment and for multi-device intercommunication. While the commercial ClearSpeed CSX700 includes a PCI Express interface and a single proprietary ClearConnect bridge (CCBR) interface, the RADSPEED DSP variant replaces the PCI Express port with a second CCBR. The inclusion of two CCBR buses allows “daisy-chaining” of the DSPs for increased processing performance. BAE Systems performed radiation hardening of the device through circuit and physical design modifications combined with the process hardening features available in BAE Systems’ RH90 90nm CMOS technology. The modifications required to achieve radiation hardening resulted in the decision to decrease the number of processing elements from 192 to 152 active processing cores, and the speed changed from 250 MHz to 233 MHz. These changes reduced the peak processing performance from 96 GFLOPS to 70 GFLOPs while keeping the power dissipation to 15W. The high performance bandwidth of the individual buses is maintained at the ~4GB/s. Figure 2 shows the completed device layout.
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