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synthetic apperture radar
milstar: Nize priwedenni primeri image i movie s dowolno wisokoj razreschajuschej sposobnost'ju 100 mm dlja SAR radara w diapazonax Ka(35ghz) i Ku waznejschij wopros dlja kakoj wojni . ######################## S-300 imelo porjadka 1500 yabch . W yslowijax podriwa serii yabch w atmosfere wse eto s xoroschim chansom ne budet rabotat' Bolee wisokuju boewuju ystojchiwost' budut imet' multimegawattnie rls s bolschoj apperturoj na lampax http://www.sandia.gov/RADAR/imageryka.html kollekzija image ot 35 ghz synthetic apperture radar razr.sposobnost' 4 inches -10 sm,100 millimetr Contact: To send feedback or request information about the contents of Sandia National Laboratories' synthetic aperture radar website, please contact: Nikki L. Angus Synthetic Aperture Radar Website Owner Sandia National Laboratories Albuquerque, NM 87185-1330 (505) 844-7776 (Phone) (505) 845-5491 (Fax) nlangus@sandia.gov http://www.sandia.gov/RADAR/movies.html kollekzija video s SAR Ku band i raz sposb 300 mm
milstar: Applying a High Performance Tiled Rad-Hard Digital Signal Processor to Spaceborne Applications BAE http://www.ann.ece.ufl.edu/courses/eel6686_15spr/papers/RADSPEED.pdf On-board processing may be performed in a variety of ways including 1) specialized radiation hardened application specific integrated circuits (ASIC) with their highest performance/watt but limited functional flexibility, 2) reprogrammable field programmable gate arrays (FPGA) with higher power requirements and additional challenges in radiation mitigation and configuration storage; 3) multi-core general purpose processors (GPP) with floating point units supported by COTS infrastructure but with lower overall performance and 4) multi-core digital signal processors (DSP) optimized for signal processing applications that provide programmability and high performance at a reasonable power. The RADSPEEDTM DSP - a radiation hardened version of the ClearSpeedTM CSX700 digital signal processor – is being developed by BAE Systems to provide a high performance per watt digital signal processor for these emerging spacecraft applications. The CSX700 is a best in class device in the commercial world and is used in a variety of graphics, financial, server and other signal processing applications supported by a full set of development tools. In hardening the RADSPEED DSP, over 70% of the performance of the commercial device was retained (70 GFLOPS peak performance) with a modest decrease in processing speed (8%) and the number of processing element cores (160 from 200). The RADSPEED DSP opens up a programmable world for specialized payload applications. This includes 1) various types of RF processing, 2) radar processing with the high throughput required for both Space-Time Adaptive Processing (STAP) and Synthetic Aperture Radar (SAR) algorithms, 3) hyperspectral imaging with the need for simultaneous processing of images across a number of frequency bands, fusing data for analysis, spectral analysis for the simultaneous assessment of data across a number of frequency bands and 4) image processing including edge and object detections and the efficient distribution of a high resolution image across a series of parallel processing elements. . RADSPEED DSP DEVELOPMENT The RADSPEED DSP is a variant of the ClearSpeedTM CSX700 [5] DSP. BAE Systems and ClearSpeed Technology modified the device for the space environment and for multi-device intercommunication. While the commercial ClearSpeed CSX700 includes a PCI Express interface and a single proprietary ClearConnect bridge (CCBR) interface, the RADSPEED DSP variant replaces the PCI Express port with a second CCBR. The inclusion of two CCBR buses allows “daisy-chaining” of the DSPs for increased processing performance. BAE Systems performed radiation hardening of the device through circuit and physical design modifications combined with the process hardening features available in BAE Systems’ RH90 90nm CMOS technology. The modifications required to achieve radiation hardening resulted in the decision to decrease the number of processing elements from 192 to 152 active processing cores, and the speed changed from 250 MHz to 233 MHz. These changes reduced the peak processing performance from 96 GFLOPS to 70 GFLOPs while keeping the power dissipation to 15W. The high performance bandwidth of the individual buses is maintained at the ~4GB/s. Figure 2 shows the completed device layout.
milstar: Технический облик многоапертурного космического радиолокатора с синтезированной апертурой на основе АФАР Х-диапазона С.Л. Внотченко, А.И. Коваленко, В.В. Риман, А.В. Шишанов ОАО «Научно-исследовательский институт точных приборов», ул. Декабристов 51, 127490 Москва, Россия, Тел: (495)402-92-77, Факс(495)404-91-91, E-mail:Alexander.Kovalenko@niitp.ru http://www.mivlgu.ru/site_arch/conf/murom2010/matherials/KRL2010/section2/2.pdf В докладе рассматриваются технический облик и основные характеристики многоапертурного РСА, реализуемого на основе сегментированной поляриметрической активной фазированной антенной решётки (АФАР) Х-диапазона с применением технологий многомерного кодирования сигнала (при передаче) и цифрового формирования луча антенны (при приёме).
milstar: «Многочастотный радиолокатор разработки и производства нашего концерна «Вега» позволяет получать информацию максимально оперативно, с более качественной детализацией изображений. Поступающая на борт информация дает детальные радиолокационные изображения объектов, скрытых туманом, дымом, снегом, грунтом, растительностью», - сказал собеседник агентства. Он уточнил, что в условиях сухих песчаных почв система может получить изображение объектов, находящихся на глубине в несколько десятков метров, практически независимо от высоты летящего судна. --------------------------------------------------------- Подробнее: http://vpk-news.ru/news/25559
milstar: http://www.sandia.gov/radar/_assets/videos/solartower.mp4 http://www.sandia.gov/radar/_assets/videos/eubankgateandtrafficvideosar.mp4 http://www.sandia.gov/radar/_assets/videos/victr.mp4 http://www.sandia.gov/radar/_assets/videos/irvideosarcomparison.mp4
milstar: DRFM-Modulator for HRR-Jamming http://ftp.rta.nato.int/public//PubFullText/RTO/MP/RTO-MP-SET-080///MP-SET-080-P07.pdf ABSTRACT The Digital RF Memory (DRFM) is a key component in modern radar jamming systems. To introduce false targets in a High-Range-Resolution (HRR) radar and other high-resolution imaging radars, a new generation DRFM-system is being developed with far better range resolution and modulation properties. The DRFM also needs better performance in the D/A-converter than in the systems used today, because of the high fidelity jamming signal. This paper is a part of a Master thesis [6] and describes a new type of DRFM-modulator that uses digital signal processing in the frequency-domain for generation of false targets [1]. The modulator is able to produce a radar scene with a number of complex false targets constructed of many single reflectors with individual modulation and with a credible background. Some of the different strategies for the modulator topology will be introduced and discussed. The modulator is being implemented using parallel digital logic in a number of Field Programmable Gate Arrays (FPGA) on a single printed circuit board (PCB) for use in FFIs experimental radar jammer named EKKO II [4]
milstar: https://prezi.com/tesgt-dwnlkj/digital-radio-frequency-memory-drfm/ DRFM sozdaet dlja radara loznuju cel
milstar: microASAR is completely contained in one aluminum enclosuremeasuring 22.1x18.5x4.6 cm. The enclosure is designed to minimizespurious emissions, self-interference, and interference from outsidesources. Despite its solid metal enclosure, the entire system, includ-ing two antennas, weighs less than 3.3 kilograms. Its lightweightdesign makes it suitable for aircraft with payload restrictions, suchas UAVs https://www.researchgate.net/publication/224383932_microASAR_A_Small_Robust_LFM-CW_SAR_for_Operation_on_UAVs_and_Small_Aircraft
milstar: КОСМИЧЕСКИЙ РАДАР "КАСАТКА" ПОЗВОЛИТ В ЛЮБУЮ ПОГОДУ РАССМОТРЕТЬ МАЛЫЕ ОБЪЕКТЫ НА ПОВЕРХНОСТИ ЗЕМЛИ 14 июля 2016 г., AEX.RU - Космический радар с синтезированной апертурой "Касатка-Р" позволит в любую погоду с орбиты рассмотреть на поверхности Земли объекты размером с футбольный мяч. Высокодетальный радиолокационный комплекс (ВРЛК) нового поколения разработан АО "НИИ ТП" (входит в интегрированную структуру АО "Российские космические системы"), специалисты которого планируют к концу 2017 года завершить изготовление первого образца изделия, сообщает пресс-служба АО "РКС". ВРЛК "Касатка-Р" создается для включения в состав целевой аппаратуры наблюдения разрабатываемого АО "РКЦ "Прогресс" (Самара) космического комплекса "Обзор-Р". Его запуск намечен на 2019 год для формирования новой российской спутниковой группировки радиолокационного дистанционного зондирования Земли (ДЗЗ). Этот космический радар создается на базе широкополосной поляриметрической цифровой активной фазированной решетки (АФАР). В бортовой аппаратуре применены оригинальные методы многоканальной радиолокационной съемки Земли с применением суперсовременных технологий "цифрового формирования лучей" (Digital Beam Forming - DBF). "Применение космических аппаратов "Обзор-Р" с радаром "Касатка-Р" расширит современные возможности по наблюдению за поверхностью планеты. Возможности радиолокатора позволяют круглосуточно и независимо от погодных условий вести радиолокационную съемку поверхности планеты в X-диапазоне в интересах МЧС, Минсельхоза, Росреестра, других министерств и ведомств, а также регионов России",-сообщили в пресс-службе. Главный конструктор радиоэлектронных систем для ДЗЗ АО "НИИ ТП" Виктор Риман: "Подобных радиолокаторов на орбите пока нет, хотя работы в этом направлении активно ведутся в Европе, Канаде, Японии, Южной Корее и США. Применение технологии цифрового формирования лучей позволяет получать кадры радиолокационных изображений земной поверхности больших размеров с высоким пространственным разрешением до 0,3-1,0 м. При этом кардинально улучшаются адаптационные свойства радара за счет большей гибкости управления параметрами радиолокационной съемки. Это придаст новые качества "космическому зрению" России". В НИИ ТП уже завершили макетирование ключевых устройств ВРЛК "Касатка-Р" и приступили к их изготовлению. Одновременно создается и отрабатывается программно-математическое обеспечение радара. Завершение этих работ намечено на конец 2016 года. К этому времени НИИ ТП планирует изготовить все устройства из состава АФАР и начать сборку и полномасштабную экспериментальную отработку бортовой аппаратуры радиолокатора "Касатка-Р". Для решения этой задачи в безэховой камере предприятия уже построен новый автоматизированный комплексный стенд.
milstar: G. Hounsfield, a radar engineer, received the Nobel Prize in Medicine for applying SAR signal processing algorithms to medical data. He did “technology transfer” from radar to medici The previous medical imaging technology used x - ray film to pr oduce blurry images of bones. Hounsfield applied radar digital signal processing algorithms to medical data to produce detailed images of 2D slices through bones and soft tissue. http://www.csun.edu/~jwadams/Image_Processing.pdf
milstar: БЦВМ на процессорном модуле с Эльбрус 4С Производительность БЦВМ (при работе с 32 разрядными числами), ГФлопс Не менее 35 Программное обеспечение операционную систему «Эльбрус», драйвера носителя мезонинов Габариты (Д x Г x В), мм не должны превышать размеров 280×230×110 Масса, кг Не более 5,5 Средняя наработка на отказ в полете, ч не менее 9000 http://www.ipmce.ru/custom/path7/path1/path2/
milstar: https://groups.csail.mit.edu/cag/wss03/talks/wss03-bond.pdf MIT Lincoln Laboratory Slide-5 Missile Seeker Stream Video Processing
milstar: Specifically, we show an average performance of 39 Gigaflops/sec for 16-Megapixel and 100-Megapixel SAR images with runtimes of 0.56 and 3.76 seconds respectively. https://users.ece.cmu.edu/~franzf/papers/spie09.pdf The most computationally intensive portion of PFA SAR Image Formation is interpolation; the final 2D FFT is nearly an order of magnitude less demanding in terms of operations count. ############################################# The high operations count for interpolation comes from the fact that we must perform two FFTs per segment/secant for each range/cross-range line. SAR’s large input data sizes (over 3.4 GB in the case of the 100 Megapixel scenario) ############## Scenarios. We examined two PFA SAR scenarios. Both scenarios were derived from 6 for comparison purposes. The first scenario is 4k x 4k (16 Megapixel) in size and the second scenario is 10k x 10k (100 Megapixel). Both scenarios have longer slant ranges (24 km and 200 km respectively), fine resolution (.1 m and .3 m) and small coherent integration angles (approx. 4 ◦ and 7 ◦ ). In both cases, the input size is slightly larger than the output size on account of re-gridding. The data sets for both scenarios consist of single precision floating point complex numbers stored in an interleaved format. Methodology. Spiral was installed on and generated code for three generations of 64-bit Intel Quad Core CPUs: the 3.0 GHz 5160, the 3.0 GHz X9560, and the 2.66 GHz Core i7 920. The first two processors share the same microarchitecture (Core 2 Quad) but were fabricated using different process technologies (65 nm and 45 nm). The X9560 also boasts a faster vector shuffle unit. Intel’s first “native” Quad Core, the Core i7, is mainly distinguished by having 2–3 times the aggregate (read and write) main memory bandwidth of the Core 2 due to a triple channel, on-die memory controller. The vital L2 data cache size figure varies across our range of CPUs with capacities of 4 MB, 6 MB, and 8 MB respectively.
milstar: https://math.la.asu.edu/~kuang/LM/031014.pdf
milstar: It is well known that SAR image formation can be accomplished via a 2-D Fourier Transform, since the data colle cted represents the Fourier Sp ace of the 3-D scene being imaged [1]. However, when a large scene is imaged at a fine resolution, a simple 2-D Fourier Transform is inadequate due to target Motion Through Resolution Cells (MTRC) [2]. One technique to alleviate image smearing caused by MTRC, is known as polar format processing [3]. In general, the raw phase history data collected for the scene represents a polar raster in the Fourier domain, so polar format processing is about reformatting the data to a Cartesian grid array for efficient digital processing and image formation of the collected SAR data. In a real-time system, the po lar-to-rectangular “r e-gridding” operation is the most processing intensive. Typically, 2-D data inte rpolation techniques are used to reformat the data, although it is possible to manipul ate radar hardware to vary pulse-to-pulse waveform and sampling parameters to considerably simplify the subsequent resampling, and limit it to a 1-D operation, thereby h elping reduce some of the processing time required. Sandia radar systems are capable of this and often collect data on a trapezoidal grid that is both uniformly spaced in the range direction; and per each row, uniformly spaced in the azimuth direction. This trapezoi dal grid leads to a traditional polar format reconstruction algorithm with a simplified proce dure that is to interpolate each row in the azimuth direction to the Cartesian grid, so th at a 2-D Fast Fourier Transform (FFT) can be used to generate the image. A second reconstruction algorithm implemented for real-time polar-format processing is accomplished through a variation on the tradi tional interpolation / 2-D FFT algorithm mentioned above [4]. First, note that due to separability, the total 2-D FFT operation can be broken into a 1-D azimuth FFT and a 1-D range FFT. Therefore, the traditional polar format processing method is broken up into 3 steps. First, interpolate each row in the azimuth direction; second, perform a 1-D FFT in the azimuth direction; and third, a 1-D FFT in the range direction. The variation for the second algorithm is a changed order of operations from the above method. This change is a 1-D azimuth FFT, followed by a linear resampling in the azi muth direction, and finally a 1-D range FFT. The notable change here is the resampling in the azi muth direction is performed after the azimuth FFT. This option is available due to the li near spacing provided by the azimuth sampling of the phase history data inherent with a trapezoidal aperture. http://prod.sandia.gov/techlib/access-control.cgi/2005/057413.pdf
milstar: https://www.egr.msu.edu/classes/ece480/capstone/spring12/group05/docs/presentations/TechLecture_Team5.pdf sandia SAR resolution 100 mm
milstar: 55 Using these timings it is obvious that the GPU processed the FFT the fastest. The GPU throughput at an FFT this size is 311 times more than that of the FPGA and 3351 times faster than the CPU Multicore with 12 threads. What is missing from this data is the transfer time for the GPU to send and receive the data. This time is 69 ms for this size data. With this time added in the GPU actually becomes the slowest of all three platforms. Now, the FPGA is the f astest at 26.67 times faster than the GPU and 10.76 times faster than the CPU https://web.wpi.edu/Pubs/E-project/Available/E-project-030212-123508/unrestricted/Benchmarking_Final.pdf 57 Since this benchmark is purely mathematical based, the 336 cores and consequently the numerous A LUs of the GPU would be m ust faster in this type of computation than the 12 cores of the CPU. The only place that the CPU would be able to make up for its slower computation would be in the data transfer portion of this benchmark. In this study though, we are only looking at raw execution and not data transfer, so the GPU is much faster than the CPU in the computation of the LU Decomposition benchmark. The Speckle Reduction benchmark uses mostly partial differential equations in its computations. As described in the background section, this benchmark consists of several, sequential parts, making synchronization of these parts a necessary feature. This necessity for synchronization is what most likely allowed the CPU execution time to equal that of the GPU. In the flat out comp utational portions of this benchmark, the GPU would most likely beat the CPU due to its sheer number of available cores. Advancements in CPU pipelining, however, allow the CPU to begin the next instruction while the current one is executing. This basical ly means that the CPU has the ability to synchronize and start its next instruction at the same time. We believe that is the uniqueness of CPU pipelining that allows it to compete with the GPU in execution time for this benchmark. 4.4. Individual Results 4.4.1. GPU Specific For any GPU today the biggest area of a setback is in the area of data transfer. Until recently, and still the majority, GPUs were only on dedicated cards requiring a 58 link to the CPU and memory over a data bus. The limitation of these busses to transfer the computed data severely limits the abilities of GPUs in high performance computing. While bus speeds have come a long way since the original PCI and AGP graphics interfaces, even the newest version of PCIE limits speeds to 32 GB/sec assuming f ull utilization of every channel both upload and download
milstar: https://users.ece.cmu.edu/~franzf/papers/akin-fpga12.pdf 2D 2024*2024 DP FFT input data64 mb 461 megaflop
milstar: CATS 700 1u 12 processors 2008 0.09 micron For 2D FFTs, timing and power consumption measurements include the corner turn measurements include the corner turn • All data always starts and finishes in the off-chip DRAM csx 700 processors 2D FFT 2048*2048 26.1 FFT per second 11.3 gigaflops 2D FFT 1024*1024 154.2 FFT per second 16.2 gigaflops With 12 CSX700 processors the CATS-700 can achieve: 26,000 1024x1024 2D FFTs per second (194 GFLOPS) 300 watt power consumed
milstar: https://www.parallella.org/wp-content/uploads/2016/10/e5_1024core_soc.pdf This paper describes the design of a 1024-core processor chip in 16nm FinFet technology. The chip (“Epiphany-V”) contains an array of 1024 64-bit RISC processors, 64MB of on-chip SRAM, three 136-bit wide mesh Networks-On-Chip, and 1024 programmable IO pins. The chip has taped out and is being manufactured by TSMC. This research was developed with funding from the Defense Advanced Research Projects Agency (DARPA). The views, opinions and/or findings expressed are those of the author and should not be interpreted as representing the official views or policies of the Department of Defense or the U.S. Government The primary goal for this project is to build a parallel processor with 1024 RISC cores demonstrating a processing energy efficiency of 75 GFLOPS/Watt. A secondary goal for this project is to demonstrate a 100x reduction in chip design costs for advanced node ASICs. Significant energy savings of 10-100x can be achieved through extreme silicon customization, but customization is not financially viable if chip design costs are prohibitive. The general consensus is that it costs anywhere from $20M to $1B to design a leading edge System-On-Chip platform.[ The second Epiphany product was a 28nm 64-core SOC (“Epiphany-IV”) completed in the summer of 2011.[7] The Epiphany-IV chips demonstrated 70 GFLOPS/Watt processing efficiency at the core supply level and was the most energy-efficient processor available at that time. The chip was sampled to a number of customers and partners, but was not produced in volume due to lack of funding. At that time, Adapteva also created a physical implementation of a 1024 core 32-bit RISC processor array, but it was never taped out due to funding constraints.
milstar: When selecting an ADC for high-frequency applications, you should recall that the sampling rate must be two or more times the bandwidth of the signal to be digitized. Such a sampling rate is called the Nyquist frequency. Note that the word bandwidth is used instead of frequency. If the input signal is other than a sine wave, it’s considered to be a complex signal. An example is a pulse that’s made up of a fundamental sine wave and multiple harmonics according to the Fourier theorem. Modulated signals also contain a wide range of frequencies that must be considered when selecting a sampling rate. Consider a square wave consisting of a fundamental frequency sine wave and an infinite number of odd harmonics. To reproduce a favorable version of the original signal, it has been shown that up to the fifth harmonic must be preserved. For a 300-MHz square wave, the sampling rate must at a minimum be twice the fifth-harmonic frequency, or 3 GHz. More complex signals like radar pulses and modulated signals require similar high sampling rates to faithfully capture the signal details. ################################################ http://www.electronicdesign.com/adc/high-speed-adcs-propel-wider-bandwidth-applications
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