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Operazionnie ysiliteli ,ZAP/AZP & (продолжение)
milstar: 1941: First (vacuum tube) op-amp An op-amp, defined as a general-purpose, DC-coupled, high gain, inverting feedback amplifier, is first found in US Patent 2,401,779 "Summing Amplifier" filed by Karl D. Swartzel Jr. of Bell labs in 1941. This design used three vacuum tubes to achieve a gain of 90dB and operated on voltage rails of ±350V. ###################################################### It had a single inverting input rather than differential inverting and non-inverting inputs, as are common in today's op-amps. Throughout World War II, Swartzel's design proved its value by being liberally used in the M9 artillery director designed at Bell Labs. ######################################################################### This artillery director worked with the SCR584 radar system to achieve extraordinary hit rates (near 90%) that ####################################################################### would not have been possible otherwise.[3] ########################### http://en.wikipedia.org/wiki/Operational_amplifier
milstar: PROCESSING IN CLUTTER Background The ultimate goal of the antiship missile seeker is to generate adequate target range and angle estimate inputs to the guidance system to enable the ASM to impact the ship. Signal processing is applied to the data to better detect the ship return and to extract the measurements. Examples of this signal processing include 1. range compression, 2. Doppler processing, 3.detection, 4.target discrimination, 5. and monopulse angle estimation. http://www.dtic.mil/cgi-bin/GetTRDoc?AD=ADA430023
milstar: Эффективная площадь рассеяния в диапазоне Х конический боевой блок = 0.01 квадр .метра THAAD Средняя(1) мощность = 81 киловатт 25344*3.2 ватта коэффициент усиления антенны = 103 000 = 41 db Шумовая температура = 400° K эффективность апертуры антенны = 0.8 площадь антенны = 9.2 m^2 длина импульса = 1 миллисекунда коэффициент заполнения =0.2 PRF = 200 Сигнал/шум обнаружение = 20 Сигнал/шум дискриминация = 100 дальность обнаружение = 870 километров дальность дискриминация =580 километров ####### Сдвоенная THAAD 18.4 m^2,162 киловатт дальность обнаружение = 1460 километров дальность дискриминация =970 километров http://mostlymissiledefense.com/2012/09/21/ballistic-missile-defense-radar-range-calculations-for-the-antpy-2-x-band-and-nas-proposed-gbx-radars-september-21-2012/ Данные по THAAD для углов элевации 30 ° и более ,При углах элевации ниже 10° дальность падает в 4-5 раз . Атака в группе , подрыв ядерного блока , заход на цель на фоне вспышки остальными резко повышает шумовую температуру радара
milstar: http://www.ep.liu.se/ecp/008/posters/019/ecp00819p.pdf SUMMARY In this paper, we evaluate a new design of a previously presented (second order) tunable active X-band MMIC filter. By using a two-stage low noise amplifier in each filter section a higher filter gain and selectivity as well as a lower filter noise figure can be achieved at the expense of a smaller filter tuning range. The filter is tunable to eight different center frequencies between 7.6-8.6GHz. Typical measured data for all eight tuning states show a maximum gain that varies between 13-26dB, a 4-5dB noise figure and a spurious-free dynamic range of 58-67dB. The presented filter could potentially be utilized as an important building block to realize agile compact on-chip receiver front-ends for future adaptive X-band radar array antennas, for example. INTRODUCTION A low vulnerability to jamming signals due to electronic warfare or electromagnetic interference, for example, is of prime importance in modern radar systems. One way to achieve this is to use a frequency hopping radar where the transmitter and the receiver jump in a pseudo-random like way between different selected frequencies. To further reduce the vulnerability to jamming signals adaptive methods and digital beamforming can be adopted [1]. In future adaptive array antennas the number of transmit/receive (T/R) modules required is anticipated to be as high as several hundreds or more. To be able to realize such multi-channel radar systems in a cost-effective way size and cost of each T/Rmodule should be minimized. As a consequence of this, increased interest has been focused on the possibility of using tunable narrow-band active monolithic microwave integrated circuit (MMIC) filters to reduce the vulnerable bandwidth of frequency hopping radar receivers [2]. Compared with using a fixed frequency bandpass filter, a tunable filter may reduce the number of down-converting stages required in an agile receiver by allowing a greater down-conversion step to be made. Rejection of interfering signals that, for example, may occur at the receiver image frequency (fimage=fRF±2fIF where fRF and f IF denote the radar frequency and the intermediate frequency of the receiver, respectively) should be high enough to minimize the effect of jamming. In this paper, we focus on active filters that may be used in receiver front-ends of adaptive X-band (8-12GHz) antennas. Typical requirements for such filters can be found in [3] (see Table 1). Below, we evaluate a re-design of a tunable X-band MMIC filter originally presented in [4]. Compared with results obtained in [4], an improved performance in terms of higher gain and selectivity as well as lower noise figure is achieved. Center frequency gain (G) > 10dB Noise figure (NF) < 5 dB Input third order intercept point (IIP3) ≥ 0 dBm Spurious-free dynamic range (SFDR) ≥ 113 dB/Hz2/3 (≥ 64dB for a noise bandwidth B= 20MHz) Table 1: Typical requirements for active filters if used in receivers of adaptive X-band radar antennas.
milstar: 5.12 MULTIFUNCTIONAL RADAR SYSTEMS FOR FIGHTER AIRCRAFT 1.Real beam map 0.5 -10 mgz 2.Doppler beam sharp 5-25 mgz 3. SAR 10 -500 mgz 4.A-S range 1-50 mgz -------------------------- 5.PVU 1-10 mgz 6.TF/TA 3-15 mgz 7.Sea surface search 0.2 -500 mgz 8.Inverse SAR 5-100 mgz 9. GMTI 0.5-15 mgz 10.Fixed target track 1-50 mgz 11.GMTT 0.5 -15 mgz 12.Sea Surface track 0.2-10 mgz ------------------------------------ 13.Hi power Jam 1-100 mgz 14.CAl/A.G.C 1-500 mgz 15A-S data link 0.5-250 mgz
milstar: http://www2.l-3com.com/eti/downloads/aoc_paper_placard.pdf Affordable High Performance Broadband Scanning Multi-Beam Antenna/Amplifier Subsystem
milstar: Description The ADS54J60 is a low-power, wide-bandwidth, 16-bit, 1.0-GSPS, dual-channel, analog-to-digital converter (ADC). Designed for high signal-to-noise ratio (SNR), the device delivers a noise floor of –159 dBFS/Hz for applications aiming for highest dynamic range over a wide instantaneous bandwidth. The device supports the JESD204B serial interface with data rates up to 10 Gbps, supporting two or four lanes per ADC. The buffered analog input provides uniform input impedance across a wide frequency range while minimizing sample-and-hold glitch energy. Each ADC channel optionally can be connected to a wideband digital down-converter (DDC) block. The ADS54J60 provides excellent spurious-free dynamic range (SFDR) over a large input frequency range with very low power consumption. The JESD204B interface reduces the number of interface lines, allowing high system integration density. An internal phase-locked loop (PLL) multiplies the ADC sampling clock to derive the bit clock that is used to serialize the 16-bit data from each channel. Features 16-Bit Resolution, Dual-Channel, 1-GSPS ADC Noise Floor: –159 dBFS/Hz Spectral Performance (fIN = 170 MHz at –1 dBFS): SNR: 70 dBFS NSD: –157 dBFS/Hz Price 706 $ P cons -2.7 watt V pp -1.9 v http://www.ti.com/product/ADS54J60 Data latency(1): ADC sample to digital output 134 input clock cycles ##############################################
milstar: http://www.analog.com/media/en/technical-documentation/data-sheets/AD9625.pdf ad9625 2.5-2.6 gsps 12 bit Vpp -1 v 100 ohm ,1.5 pf Pdiss -4 watt Fin 1 ghz ,ENOB = 9.1 bit ,SFDR -79 dbc (!) FAST DETECT OUTPUT (FD) Latency Full 82 Clock cycles ######################### Pipeline latency 226 glock cycles aperture delay -200 ps
milstar: ADC12D1800RF http://www.ti.com/lit/ds/symlink/adc12d1800rf.pdf Vpp -0.8-1 v Cin -1.6 pf Rin -100 ohm P consump -4.7 watt Fclk -1.8 ghz aperture jitter -0.2 ps Latency t lat -34 sampling clock cycles -------------------------------------------
milstar: Low latency ADC 3 stage pipeline TI 12-Bit, 1-GSPS Analog-to-Digital Converter http://www.ti.com/lit/ds/symlink/ads5400.pdf Latency 7.5-8.5 cycles Apperture delay- 250 ps Jiter -125 fs ------------------------- E2V folding interpolation SiGe 0.18 micron 200 ghz pprocess http://www.e2v.com/resources/account/download-datasheet/1784 EV12AS200ZPY 12-bit 1.5 Gsps ADC The EV12AS200 works in fully differential mode from analog inputs through digital outputs. It operates in the first Nyquist zone up to L-Band. Rin =100 ohm,0.3 pf Pin -0.5v pp latency -5 cycles apperture delay -75 ps jitter -100 fsrms output data pipeline delay -4-5 cycles TPD -Number of clock cycles between the sampling edge of an input data and the associated output data being made available, (not taking in account the TOD). (TOD) Digital data Output delay Delay from the rising edge of the differential clock inputs (CLK, CLKN) (zero crossing point) to the next point of change in the differential output data (zero crossing) with specified load. (TDR) Data ready output delay Delay from the falling edge of the differential clock inputs (CLK, CLKN) (zero crossing point) to the next point of change in the differential output data (zero crossing) with specified load.
milstar: military product http://www.appliedradar.com/Datasheets/AR8005.pdf AR8005 Four Channel 1.5 GSPS 8-Bit ADC Single Mezzanine Module The AR8005 ADC chipset allows for either baseband or second Nyquist band real-time sampling of analog IF or RF signals with over 500 MHz of instantaneous bandwidth and 7.5 effective bits. A single onboard PLL clock is used to clock all four ADC channels
milstar: An additional advantage of SiGe-based devices is their low latency, an important feature for bandwidth-sensitive EW applications. ---------------------------------------------------------------------------------------- http://mil-embedded.com/articles/sige-based-warfare-processing-performance/ The new SiGe-based generation of ADCs is delivering the next big performance leap, doubling bandwidth speeds up to 12 GSps. For EW applications, the benefit is straightforward: The higher sample rates and associated bandwidth ensure better spectrum coverage and improved Probability Of Intercept (POI) for signals of interest. In addition, the performance of these 8-bit parts surpasses off-the-shelf 10-bit ADCs in terms of Spurious Free Dynamic Range (SFDR). Typically, a first pass of the spectrum segment is done at high bandwidth to pull in as much data as possible to obtain areas of interest to analyze, after which a higher-resolution, lower-bandwidth solution is leveraged to focus on specific targets. As warfighters see a far greater range of the spectrum, more lives are saved and mission success probability is increased because of faster, more accurate identification of threats and improved response options. An example of an OpenVPX board that delivers the latest generation of devices is Curtiss-Wright’s rugged CHAMP-WB-DRFM 6U card set, combining a Tektronix TADF-4300 module featuring a SiGe-based 12.5 GSps 8-bit ADC and a 12 GSps 10-bit DAC (Figure 1), on a Xilinx Virtex-7 FPGA-based 6U VPX card, the CHAMP-WB.
milstar: This new offering uses an analog-to-digital converter (ADC) from Tektronix that samples at 12 GSamples/s to digitize a bandwidth of 6 GHz. This single-board solution also features a 12-GSamples/s digital-to-analog converter (DAC)at its output, and a Virtex-7 field-programmable gate array (FPGA) from Xilinx that can receive or source data at 12 GSamples/s. The CHAMP-WB-DRFM VPX board consists of Curtiss-Wright’s CHAMP-WB baseboard that contains the FPGA supported by 8 GB of DDR3L SDRAM and the TADF-4300 Enhanced FMC mezzanine card that contains the ADC and DAC that together form the CHAMP-WB-DRFM (see table). http://defenseelectronicsmag.com/systems-amp-subsystems/single-board-captures-digitizes-dc-6-ghz Using the CHAMP-WB-DRFM as the core conversion and processing portion of a digital RF memory (DRFM) in a fighter aircraft as an example, the analog signal from an antenna or downconverter is directly digitized by the ADC on the TADF-4300 and sent via LVDS to the FPGA. Customer-supplied algorithms resident in the FPGA then scour the wideband signal capture stream to find the comparatively narrowband signals from an enemy radar.
milstar: Using the CHAMP-WB-DRFM as the core conversion and processing portion of a digital RF memory (DRFM) in a fighter aircraft as an example, the analog signal from an antenna or downconverter is directly digitized by the ADC on the TADF-4300 and sent via LVDS to the FPGA. Customer-supplied algorithms resident in the FPGA then scour the wideband signal capture stream to find the comparatively narrowband signals from an enemy radar. These cards support commercial applications such as direct RF digitization, ground-penetrating radar (GPR) and coherent optical applications, as well as enabling deployed defense and aerospace, sense & response applications that require wideband capability and low latency, such as DRFM, EW, Signal Intelligence (SIGINT), and Electronic Counter Measures (ECM). http://vita.mil-embedded.com/news/curtiss-wright-electronic-warfare-applications/ The TADF-4300 module supports sampling in the 2nd nyquist zone, to analyze signals up to 8 GHz and provides sub-30 ns latency for the ADC and sub 10ns for the DAC. Spurious Free Dynamic Range varies over frequency, and is >58 dB up to 3 GHz and decreases to 45 dB from 3 GHz to 6 GHz signal input frequency. ENOB varies linearly from 7.2 at low frequency, 6.5 at 3 GHz and 6.2 at 6 GHz.
milstar: For example, for the stressing mission in the electronic warfare (EW), advanced electronic support measure (ESM) receivers are needed to meet the specific requirements and are expected to have the characteristics of broad instantaneous bandwidth (>1 GHz), wide spatial field-of-view, simultaneous signal processing capability, and good sensitivity and dynamic range [6]. Some limitations exist in traditional ESM receivers and need to be overcome. Those limitations include high cost, large physical size, limited programmable flexibility resulting from fixed analog hardware architecture, and analog components’ tendency to drift with time and temperature. To mitigate those problems, pushing the ADC closer to the antenna and eliminating as many analog components as possible is a trend for the design of next-generation ESM receivers. The ADC that can meet the requirements of this ESM receiver should have the capability of sampling the input signal with bandwidth greater than 3 GHz and achieving a dynamic range larger than 60 dB (> 10 bits) file:///C:/Users/gast/Downloads/li_xiangtao_200808_phd.pdf Table 2: Key Specifications of SiGe HBT (npn) BiCMOS Technologies Offered by IBM Microelectronics
milstar: Ridgetop’s radiation-hardened programmable SiGe analog-to-digital data converter (ADC) has fast digitization with extremely high linearity and dynamic range to achieve system performance targets. In many applications, with the added requirement of radiation hardness and low power, the ADC is a critical chokepoint that must meet demanding standards. Accordingly, Ridgetop’s ADC is highly linear with an INL and DNL of no more than ±0.5 LSB, an operating temperature range of at least -10 to 80 °C, a very high effective number of bits (ENOB) of 11.0, and a total ionizing dose (TID) rating of 1 Mrad. The ADC employs an innovative time-interleaved pipeline architecture and is based on the advanced silicon-germanium (SiGe) bipolar complementary metal oxide semiconductor (BiCMOS) General Description ■ Time-interleaved pipeline architecture ■ 500 MS/s to 3 GS/s sampling speed ■ 12-14 bits resolution, programmable (11-12 bits ENOB) ■ SiGe BiCMOS technology ■ Uses 77% less power than commercially available ADCs technology, providing an effective number of bits more than 2 bits higher (ENOB = 11.0 bits) than the best commercially available 3 GS/s ADC. http://www.ridgetopgroup.com/wp-content/uploads/2015/06/PB_RGADC-14B-3G-RH.pdf
milstar: A single-core architecture also has advantages in terms of latency. Fore examples, latencies as low as 3 clock cycles as found with the EV12AS200 [2] are very useful in applications such as EW and tracking systems. ######## http://www.embedded.com/print/4370321
milstar: folding -interpolation ADC по русски КМОП-АЦП со складывающей (folding) архитетурой, которая... https://docviewer.yandex.ru/?url=http%3A%2F%2FCyberLeninka.ru%2Farticle%2Fn%2Fvysokoskorostnoy-bezkondensatornyy-kmop-atsp-s-interpoliruyuschimi-zaschelkami-i-reversiruemym-taktirovaniem.pdf&name=vysokoskorostnoy-bezkondensatornyy-kmop-atsp-s-interpoliruyuschimi-zaschelkami-i-reversiruemym-taktirovaniem.pdf&lang=ru&c=568e58d6ede3&page=1
milstar: Simplify the Routing Multi-gigasample converters with 10-, 12-, or 14-bit resolution generate lots of output data, and in a hurry. The use of low-voltage differential-swing (LVDS) data could require 30 parallel lanes of 1-Gbit/s data for a 2.5-Gsample/s, 12-bit ADC. Handling 30 differential LVDS pairs per ADC can be challenging to route and maintain matched lengths on a system layout. Equivalent data can be sent with only six or eight differential lanes using JESD204B, a high-speed serializer/deserializer (SERDES) standard designed specifically for converter interfaces. JESD204B provides a means to output data at high speeds on fewer data lines without the matched timing board complexities of many high-speed LVDS lanes. Since the data sent over JESD204B is framed, based on an embedded clock and control characters, the routing of the lower-count serial lanes is much more forgiving of timing skew than LVDS (Fig. 2). This removes the need to spend countless hours working to tweak output timing on every I/O of the system PCB. http://electronicdesign.com/analog/gigasample-adcs-promise-direct-rf-conversion Over-Range Detection Adaptive gain algorithms are important in terms of adjusting the amplitude of an analog input signal, since a saturated ADC input essentially makes the system blind in its ability to decipher signals. Ideally, the gain adaptation feedback loop should be as fast as possible. Whether the high-speed ADC output is LVDS-based or uses JESD204B, the added latency of this digital output often can be too long to wait to receive the saturated data, detect the issue, and react to the condition. One solution to this issue is to use a variable-level comparison within the ADC core itself and directly send an immediate output flag upon occurrence of an over-range condition. This technique bypasses the latency of the longer back-end output stage, which shortens the feedback time to the amplifier, allowing for a faster adaptive gain cycle. In addition to this “fast over-range detection” output, the over-range samples can be appended with alert bits, using the JESD204B interface, to let downstream system processing make appropriate decisions about the data. For high-sample-rate systems that don’t need to observe a large frequency spectrum, digital downconversion (DDC) allows a sub-sampling and filtering strategy for decimating the amount of data output from the gigasample-per-second ADC. Downstream processing then observes a smaller portion of the frequency spectrum.
milstar: Data Compression in Radar Systems Introduction An application note describing an efficient method for real time compression of digital data and its application to radar systems Problem One of the most significant developments in radar technology since its first deployment over seven decades ago has been the conversion from analog (RF) to digital for signal processing, transfer, and storage. Solid state technology with digital processing, ultrafast analog to digital converters, commercial microprocessors, digital signal processing (DSP) chips, field-programmable gate arrays (FPGAs), and high speed digital networking have provided the capability of handling radar signal processing in the digital realm. Digitization has led to increasingly fast and efficient processing, broad new opportunities for offering radar sensor information on the tactical internet, as well as innovative ways to display radar information. In addition, multifunctional radar systems are becoming commonplace, increasing the need for sophisticated and powerful data management strategies. With dynamic range and sampling rates on the rise, powerful algorithms demanding more and accurate data, and system architectures becoming increasingly sophisticated, the problems of data bandwidth limitations and storage bottlenecks have come to the forefront of many system designs. These bandwidth issues have the potential to limit system performance if not managed properly. Solution: Real-time data compression Moog is a supplier of high-bandwidth slip rings, fiber optic rotary joints, positional feedback devices, and sophisticated sub-systems for radar (both ground-based and airborne) systems. Samplify®, Inc. is a company that has developed an efficient method for compressing sampled analog signals in real time http://www.globalspec.com/MoogComponents/REF/Note_230_DataComRadar.pdf
milstar: DRFM-Modulator for HRR-Jamming http://ftp.rta.nato.int/public//PubFullText/RTO/MP/RTO-MP-SET-080///MP-SET-080-P07.pdf ABSTRACT The Digital RF Memory (DRFM) is a key component in modern radar jamming systems. To introduce false targets in a High-Range-Resolution (HRR) radar and other high-resolution imaging radars, a new generation DRFM-system is being developed with far better range resolution and modulation properties. The DRFM also needs better performance in the D/A-converter than in the systems used today, because of the high fidelity jamming signal. This paper is a part of a Master thesis [6] and describes a new type of DRFM-modulator that uses digital signal processing in the frequency-domain for generation of false targets [1]. The modulator is able to produce a radar scene with a number of complex false targets constructed of many single reflectors with individual modulation and with a credible background. Some of the different strategies for the modulator topology will be introduced and discussed. The modulator is being implemented using parallel digital logic in a number of Field Programmable Gate Arrays (FPGA) on a single printed circuit board (PCB) for use in FFIs experimental radar jammer named EKKO II [4]
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