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Operazionnie ysiliteli ,ZAP/AZP & (ïðîäîëæåíèå)
milstar: 1941: First (vacuum tube) op-amp An op-amp, defined as a general-purpose, DC-coupled, high gain, inverting feedback amplifier, is first found in US Patent 2,401,779 "Summing Amplifier" filed by Karl D. Swartzel Jr. of Bell labs in 1941. This design used three vacuum tubes to achieve a gain of 90dB and operated on voltage rails of ±350V. ###################################################### It had a single inverting input rather than differential inverting and non-inverting inputs, as are common in today's op-amps. Throughout World War II, Swartzel's design proved its value by being liberally used in the M9 artillery director designed at Bell Labs. ######################################################################### This artillery director worked with the SCR584 radar system to achieve extraordinary hit rates (near 90%) that ####################################################################### would not have been possible otherwise.[3] ########################### http://en.wikipedia.org/wiki/Operational_amplifier
milstar: LTC2107 PGA= 0 p-p 2.5 v,PGA =1 p-p 1.6v 141 mhz -1 dBFS SINAD 78.7 db, 76.7 db SFDR 2hd harm. 87.5db 95.5 db http://cds.linear.com/docs/en/datasheet/2107fb.pdf
milstar: AV107 Phased-Array Radar-Receiver EW-ESM AV107 Phased-Array Radar-ReceiverEW-ESM AV121 Phased-Array Radar Receiver EW-ESM MIMO http://www.apissys.com/products
milstar: LTC2387 18 bit 15 msps http://cds.linear.com/docs/en/datasheet/238718fa.pdf 1mhz SINAD -94.5db SFDR -102 db
milstar: How to Oversample 5 MSPS, 18-Bit/16-Bit Precision SAR Converters to Increase Dynamic Range by Maithil Pachchigar http://www.analog.com/media/en/technical-documentation/application-notes/AN-1279.pdf The AD7960 and AD7961 data sheets list a typical dynamic range of 100 dB and 96 dB, respectively, using a 5 V reference. Therefore, in theory, oversampling by 256× increases the dynamic range by 24 dB. In reality, the measured oversampled dynamic range of these devices is 123 dB and 120 dB, respectively (see Figure 5 and Figure 7), with no input signal when oversampled by 256× at an output data rate of 19.53 kSPS
milstar: http://www.intersil.com/content/dam/Intersil/documents/isla/isla216s.pdf intersil isla216 16-Bit, 250/200/130 MSPS JESD204B High Speed Serial Output ADC 250 msps ain -2dbfs --------------------------- Fin 190 mhz ENOB 11.95 bit SINAD-73.9 db SFDR -82 db -------------------- http://www.analog.com/media/en/technical-documentation/data-sheets/AD9467.pdf ad9467-200/250 msps fin 170 mhz Ain -1dbfs SINAD-74.1/75.6 db SFDR -95/90 db ENOB 12/12.3bit -------------- LTC2107 http://cds.linear.com/docs/en/datasheet/2107fb.pdf Ain -1dbfs 141 mhz SINAD -78.7/76.7 db SFDR -87.5/95.5 db
milstar: Comparison of GS/s Analog-to-digital Converters Enhanced by ADX4 http://spdevices.com/index.php/adx4-comparison
milstar: http://spdevices.com/index.php/linearization Linearization of ADCs - ADL
milstar: ENOB 13 bit by BW 10 mhz e2v 12bit as200 http://www.embedded.com/print/4370321 System performance The performance of the system can be enhanced even further using post processing and real-time techniques, such as integral nonlinearity (INL) correction and using dither to improve SFDR. The shape of the INL curve plays a large part in the harmonic performance of the ADC. By characterizing this INL and using a look-up table (LUT) in the interface FPGA, the INL can be minimized, which brings benefits for the SFDR performance. The look-up table correction is a simple subtraction or addition of the measured INL value for the code. Using this technique has very little impact on the size of the FPGA and no impact on throughput. In some cases, the addition of a LUT for INL correction can improve SFDR by 10dB. The SFDR can also be improved by adding an out-of-band noise source to the input data. This can simply be a low-pass-filtered noise generator added to the input signal using a multi-port transformer. This has the effect of moving the input signal around the input scale of the ADC, which reduces the INL effect and improves SFDR (see Figure 4).
milstar: http://cds.linear.com/docs/en/datasheet/238718fa.pdf 15Msps Throughput Rate n No Pipeline Delay, No Cycle Latency n 95.7dB SNR (Typ) at fIN = 1MHz n 102dB SFDR (Typ) at fIN = 1MHz n Nyquist Sampling Up to 7.5MHz Input
milstar: http://www.analog.com/media/en/technical-documentation/data-sheets/AD9625.pdf str.33 The AD9625 architecture includes two DDCs, each designed to extract a portion of the full digital spectrum captured by the ADC. Each tuner consists of an independent frequency synthesizer and quadrature mixer; a chain of low-pass filters for rate conversion follows these components. Assuming a sampling frequency of 2.500 GSPS, the frequency synthesizer (10-bit NCO) allows for 1024 discrete tuning frequencies, ranging from −1.2499 GHz to +1.2500 GHz, in steps of 2500/1024 = 2.44 MHz. The low-pass filters allow for two modes of decimation. • A high bandwidth mode, 240 MHz wide (from −120 MHz to +120 MHz), sampled at 2.5 GHz/8 = 312.5 MHz for the I and Q branches separately. The 16-bit samples from the I and Q branches are transmitted through a dedicated JESD204B interface. • A low bandwidth mode, 120 MHz wide (from −60 MHz to +60 MHz), sampled at 2.5 GHz/16 = 156.25 MHz for the I and Q branches separately. The 16-bit samples from the I and Q branches are transmitted through a dedicated JESD204B interface. By design, all of the blocks operate at a single clock frequency of 2.5 GHz/8 = 312.5 MHz. Each filter stage includes a gain control block that is programmable by the user. The gain varies from 0 dB to 18 dB, in steps of 6 dB .... Filter performance is shown in Figure 83 and Figure 84. The filter yields an effective bandwidth of 120 MHz, with a transition band of 156.5 MHz − 120 MHz = 36.5 MHz. Therefore, the two-sided complex bandwidth of the filter is 240 MHz. A rejection ratio of 85 dB ensures that the seven aliases that fold back into the pass band yield an SNR of 85 dB − 10log10(7) = 76.5 dB, which ensures that the aliases remain sufficiently below the noise floor of the input signal. The pass-band ripple is ±0.05 dB, as shown in Figure 84.
milstar: Three e2v space grade data converter families have been awarded QMLV certification from the U.S. Defense Logistics Agency (DLA). The QMLV space certification will make it even easier for global space programs to adopt e2v’s world leading data converters. The certification, awarded to one Analog-to-Digital (ADC) and two Digital-to-Analog (DAC) families, reduces the amount of time and investment required by customers to test these e2v products. Richard Gibbs, president of e2v Semiconductors, said, “QMLV product listing is becoming more and more important to our customers as it significantly reduces their testing time. The certification of these products shows our commitment to the space industry and contributes towards the building of a comprehensive QML semiconductor portfolio.” With over 3,000 e2v data converter flight models currently in space, the ability to reduce customer testing time by almost 50 percent will further expand e2v’s semiconductor space presence. The newly certified products are all true single core devices, providing outstanding linearity and microwave capability for software defined RF systems in space. Suitable applications for these data converters include satellite communications, SAR imaging, GNSS navigation satellites and other forms of scientific space-borne instruments. The QMLV listing of these parts, in addition to the QMLV ratings of e2v’s manufacturing facilities in France and the United States, reinforces e2v’s commitment to the space market. e2v played a significant role in defining the recently released QMLY certification, working closely with NASA, and these particular ADCs and DACs already appear on the European Space Agency’s preferred parts list. November 9, 2015 http://www.microwavejournal.com/articles/25447-e2v-space-grade-data-converters-receive-qmlv-certification
milstar: A single-core architecture also has advantages in terms of latency. Fore examples, latencies as low as 3 clock cycles as found with the EV12AS200 [2] are very useful in applications such as EW and tracking systems. http://www.embedded.com/print/4370321 wo key specifications that are important for ADCs that serve in L-band applications are spectral purity and noise floor. Spectral Purity A true single-core architecture has significant advantages because it does not rely on internal interleaving to achieve a 1.5GS/s update rate. Hence, no form of calibration is required before or during operation over an extended temperature range. (One feature of interleaved ADCs is their prominent interleaving spurs. The offset mismatch will produce a spur of a fixed frequency; however, gain and phase mismatches will produce spurious frequencies that depend on the input signal frequency. Indeed, calibration is sometimes requested in ADCs using internal interleaving to avoid spurious free dynamic range performance degradation due to misalignment of gain, offset, and sampling aperture delays. ) The single-core advantage can be seen in the spectral purity plot shown in Figure 2. The choice of the frequency is made so that the main signal and its harmonics are close together in the FFT plot. This leaves the rest of the spectrum free to display any other non-signal related spurious signals for example clock spurs. An interleaved ADC may well display spurs in this region but we can see that he signal core shows a spur free zone and a spectral purity of 90dBc. A single-core architecture also has advantages in terms of latency. Fore examples, latencies as low as 3 clock cycles as found with the EV12AS200 [2] are very useful in applications such as EW and tracking systems.
milstar: Another important feature is the input voltage full scale range. The harmonic performance of the ADC is so low that the system performance could be badly affected by poor spurious levels on the input driver. This problem is reduced if the ADC can accept a low input voltage. The EV12AS200 has an input voltage range of 500mVpp.
milstar: The AD9625 is the only open-market-available 12-bit, 2-GSPS, A/D converter that simplifies the digital interfacing challenge by integrating two digital-down converters (DDC), two numerically controlled oscillators (NCO) and a configurable JESD204B serial link for the output data. These industry firsts improve usability and functionality by reducing output data rate requirements and simplifying board-level design and layout. Key applications include ultra-wideband RADAR, wideband front-ends for digital storage oscilloscopes and data acquisition platforms. http://redesign.automation.com/product-showcase/analog-devices-releases-ad9625-ad-converter
milstar: AD9625 12-bit A/D Converter Features Exclusive Among Gigasample ADCs Best AC Parametric Performance: 56dB of SNR and 75dBc SFDR up to 1.8GHz input frequency Smallest Form Factor 12x12 mm2 196 BGA 80% smaller than the ADC12D1800RF Higher Levels of Integration, Functionality http://de.slideshare.net/AnalogDevicesInc/ad9625-12bit-2-5-gsps-analogtodigital-converter
milstar: http://www.ll.mit.edu/HPEC/agendas/proc09/Day2/S4_1405_Song_presentation.pdf -------- In order to prevent the spurs and intermods from interfering with small signal detection, the linearity needs to be enhanced to reduce the spur and intermod levels. MIT Lincoln Laboratory has developed the nonlinear equalization (NLEQ) and Time Varying Quantization (TVQ) technologies to enhance linearity of mixed-signal sensor systems. The NLEQ technique can digitally model the ADC nonlinearities and subtract them out from the digitized output to suppress the spur and intermod levels. However, because NLEQ algorithm can only suppress low-order nonlinearities, linearity improvements have often been limited until recently. The new TVQ technology can achieve significantly higher linearity by suppressing high order nonlinearities that the NLEQ technique cannot address. An especially designed additive signal (TVQ signal) is inserted at the input of the ADC. The TVQ signal is designed to minimize the coherent integration of spurs and intermods, including high-order spurs/intermods that are difficult to equalize. The resulting digitized signal mainly contains low-order nonlinearities that are then be attenuated by the NLEQ technique. The preliminary experimental results indicate up to four orders of magnitude higher spur-free dynamic range (SFDR) and intermod-free dynamic range (IFDR) may be possible with the linearity enhancement techniques. This means that sensors would be able to operate properly in environments with a ten thousand times higher interference signals. We believe that many commercial and military applications could benefit from the TVQ/NLEQ technology especially for systems that need to operate in challenging environments. Dr. William S. Song is a senior staff member in the Embedded and Open Systems Group at MIT Lincoln Laboratory. He received his B.S., M.S., and Ph.D. degrees from the Massachusetts Institute of Technology in 1982, 1984, and 1989, respectively. Since his arrival at Lincoln Laboratory in 1990, Dr. Song has been working on high-performance sensor and VLSI signal processor technologies for various applications. He has developed numerous advanced signal processing algorithms, architectures, real-time embedded processors, and sensor array systems. Recently, he has been working on the graph processor, communications processor, linearity enhancement techniques, mixed-signal system on chip, high-throughput low-power VLSI signal processors, and highly digitized wideband sensor arrays. Dr. Song has been the technical director for a number of programs, including the cooperative communication processor, graph processor, wideband linearity enhancement processor, X-band element-level digitized sensor array, receiver-on-chip, space-based radar onboard signal processor, high-dynamic-range digital receiver, adaptive digital beamformer processor, and miniaturized mixed-signal receiver/processor programs. He has also designed a series of high-performance special-purpose signal processor ICs for these applications. His accomplishments include 14 U.S. patents with 1 more pending, 24 invention disclosures, and 28 journal and conference publications. He received MIT Lincoln Laboratory Technical Excellence Award in 2006. He is also an IEEE Senior Member. http://ieeeboston.org/event/receiver-linearity-enhancement-techniques/
milstar: http://www.electronicproducts.com/Videos/Arrow_Product_Insights_Analog_Devices_AD9625_HMC7044_and_ADA4961.aspx video
milstar: With stretch processing we are limited to a range extent that is usually smaller than an uncompressed pulse width. Thus, we couldn’t use stretch processing for search because search requires looking for targets over a large range extent, usually many pulse widths long. --------------------------------------------------- We could use stretch processing for track because we already know range fairly well but want a more accurate measurement of it. We must point out that, in general, wide bandwidth waveforms, and thus the need for stretch processing, is “overkill” for tracking. Generally speaking, bandwidths of 1s to 10s of MHz are sufficient for tracking -------------------------------------- One of the most common uses of wide bandwidth waveforms, and stretch processing, is in discrimination, ------------------------------------------------------------------------------------- where we need to distinguish individual scatterers on a target. Another use we will look at is in SAR (synthetic aperture radar). Here we only try to map a small range extent of the ground but want very good range resolution to distinguish the individual scatterers that constitute the scene. http://www.ece.uah.edu/courses/material/EE710-Merv/Stretch_11.pdf
milstar: 25.2 blocksxema priemnika radara http://jocoleman.info/pubs/papers/SkolnikCh25.pdf Direct Digital Downconversion. If the designer has some flexibility in either the IF center frequency or ADC sample rate, a simplified DDC architecture, direct digital downconversion, can be considered.4,5 If the ADC sample rate is four times the center of the IF band, then the sampling process can also shift the spectrum to baseband, and the NCO and associated multipliers of the general DDC are not needed. In general, direct conversion to baseband is a simple and cost-effective DDC method that can be used when the signal being sampled is always centered at a single frequency. The standard DDC architecture might need to be used when the center frequency of the signal being sampled dynamically changes, which forces the DDC’s LO to change accordingly.
milstar: http://www.ridgetopgroup.com/products/semiconductors-for-critical-applications/instacell-ip-core-library/analog-to-digital/#RGADC-14B-3G-RH Time-interleaved pipeline architecture 500 MS/s to 3 GS/s sampling speed 12-14 bits resolution, programmable (11-12 bits ENOB) SiGe BiCMOS technology Uses 77% less power than commercially available ADCs Two configurable pipeline channels Four programmable operation modes Hard to 1 Mrad TID Hard to 120 MeV-cm2 /mg SEL
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