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Operazionnie ysiliteli ,ZAP/AZP & (продолжение)
milstar: 1941: First (vacuum tube) op-amp An op-amp, defined as a general-purpose, DC-coupled, high gain, inverting feedback amplifier, is first found in US Patent 2,401,779 "Summing Amplifier" filed by Karl D. Swartzel Jr. of Bell labs in 1941. This design used three vacuum tubes to achieve a gain of 90dB and operated on voltage rails of ±350V. ###################################################### It had a single inverting input rather than differential inverting and non-inverting inputs, as are common in today's op-amps. Throughout World War II, Swartzel's design proved its value by being liberally used in the M9 artillery director designed at Bell Labs. ######################################################################### This artillery director worked with the SCR584 radar system to achieve extraordinary hit rates (near 90%) that ####################################################################### would not have been possible otherwise.[3] ########################### http://en.wikipedia.org/wiki/Operational_amplifier
milstar: SAR: Range Resolution http://www.eecis.udel.edu/~xma/ELEG467_667/SAR%20FINAL.pdf
milstar: http://www.afc-ingenieros.com/uploads/Afc/InfoTecn/RTSA/pdf/17%20Advanced%20Radar%20Analysis%2037W23378-0.pdf
milstar: Radar Digital Signal Processing James J. Alter Jeffrey O. Coleman Naval Research Laboratory http://www.mhprofessional.com/downloads/products/0071485473/SkolnikCh25.pdf
milstar: Stretch Processing ,str 9 ################### http://www.eecis.udel.edu/~xma/ELEG467_667/SAR%20FINAL.pdf – “De-ramp” received signal by mixing with a longer reference signal of the same chirp rate • Target returns are “beat frequencies” • A/D rate directly related to range window extent and low pass filter • Reduced sampling requirements eases downstream processing – The frontend hardware must support the additional RF bandwidth required for the “de-ramp reference” ---------------------- str.64 Recall: – Most SARs use Stretch Processing to deramp the transmitted pulse • Eases hardware and processing constraints • Also allows us to analyze SAR data as a projection of a 2 dimensional scene into a one dimensional function – Similar to Tomography!! – Let’s take a look at the stretch waveform and its output
milstar: Synchronous Detector http://www.radartutorial.eu/10.processing/sp06.en.html http://spiedigitallibrary.org/proceedings/resource/2/psisdg/2747/1/98_1?isAuthorized=no The combination of IF sampling and stretch processing is advantageous because A/D samplers are now able to operate at adequately short sample- and-hold aperture times, for use at IF frequencies, with a good number of bits resolution, and stretch processing can use narrow IF bandwidths. Therefore, high range resolution can be achieved at a lower cost than with quadrature channels at baseband and dual A/D's. Added benefits are the elimination of I-Q imbalance effects, A/D DC offset effects, and the need for calibration of these effects. Some A/D saturation can also be tolerated.
milstar: Understanding State of the Art in ADCs © 2008 Brad Brannon, Analog Devices, Inc. What http://www.converter-radio.com/understandingSOA.pdf
milstar: What are the Hardest Limitations? A number of limitations exist in data converters. As mentioned above, there is a natural conflict between SNR and SFDR. These are improved by advances in architecture and optimizations in process. While improvements have continually occurred over time, the process is at least partially reset each time a new semiconductor process is employed (see above). Because of this, improvements often tend to be two steps forward and one step backwards. Cost pressures push decisions to switch to newer processes whereas remaining on older processes would indicate that generational improvements in performance are possible but not necessarily a cost reduction http://www.converter-radio.com/understandingSOA.pdf
milstar: While there is a clear need for fullscale performance in the range of -110 to -120 dBFS, consistent performance of only -95 to -100 dBFS is available in the baseband region today. At the same time great attention has been paid to increasing SFDR performance in the mid and high IF regions with a result that usable IF frequencies as high as 450 MHz are not uncommon for some applications. How do we get there? Because of the physics of ADCs, there will always exist a natural opposition between spurious performance and SNR. Therefore, designers are constantly forced to compromise one specification for another. Therefore, it is key for Understanding State of the Art in ADCs Page 16 of 20 http://www.converter-radio.com/understandingSOA.htm 1/9/2012 customers to give feedback and guidance to ADC manufacturers. Without clear direction, ADC manufactures will move in the direction they are most drawn to which may not be the direction most needed by the customer. Clearly however, a focus needs to be placed on fullscale and near fullscale spurious performance. This will come in time but the issue is continually compounded by process changes that require lower power supplies
milstar: http://www.converter-radio.com/IIC2003.pdf Software Defined Radio, the new reality Brad Brannon & David Buchanan Analog Devices, Inc. Greensboro NC, USA
milstar: http://www.emrsdtc.com/conferences/2007/downloads/pdf/conference_papers/A023.pdf Dynamic Range Enhancements in Radar Sensors B. J. Harker, Z. Dobrosavljevic, E. P. Craney, S. Miles, R. A. Belcher* and J. Chambers* Roke Manor Research Ltd, Roke Manor, Romsey, Hampshire, SO51 0ZN, UK *Cardiff University, Centre of DSP, Wales, CF24 0YF, UK http://www.roke.co.uk, brett.harker@roke.co.uk © 2007 Roke Manor Research Ltd
milstar: re: Understanding State of the Art in ADCs © 2008 Brad Brannon, Analog Devices, Inc. What http://www.converter-radio.com/understandingSOA.pdf From:"Brannon, Brad" Analog Device To milstar Date:Sun, 15 Jan 2012 6:54 PM (15 hours 20 minutes ago) Show Raw MessageShow full header Sir Thank you for your inquiry and the references. I looked through them. They seem interesting. As for the converters, while I am not aware of any commercial technology right now, this technology seems feasible. Here is what I see today based largely on public domain information similar to those references you provided. SNR in 20 MHz BW with a sample rate of about 125 MSPS can approach the mid-80s. this seems consistent with what you have asked. As for SFDR, this is the difficult spec to hit. While these numbers are easily achievable for baseband (audio) converters, maintaining this kind of performance into the IF bands is very difficult. As some of your papers point out there are numerous digital techniques to linearize converters. We are certainly familiar with a number of these. Unfortunately as is apparent, this comes at the penalty of higher power. I would say that right now to achieve consistent performance above 100 dB at 70 MHz would be less than 5 watts. Perhaps 2-3 is possible. One key setback right now is customers are not willing to add the price of the current digital logic or dissipate the extra power to achieve this. However, I will say that as converters move to 65 nm and smaller geometries both cost and power will continue to fall enabling these kinds of features to be standard on many standard converter products. Stay tuned over the next 2 years or so. It probably will happen. As for the 20-24 bit question, that is more difficult to say at this point. I would guess this is 5-10 years before commercial products are available. Also, I'm not sure about the noise numbers. These may well be below what is possible from a thermal noise point of view. Regards, Brad ################## To: Brannon, Brad Subject: Fwd-2: 18 bit ADC, Fin 70 mhz ,20 mhz, 80-100 msps ,SFDR 100+ dBFS ,SNR 80+db by input -1 dbFS , Is is possible today ?/P.S. http://highfrequencyelectronics.com/Archives/May08/HFE0508_Cannata.pdf http://www.ll.mit.edu/HPEC/agendas/proc09/Day2/S4_1405_Song_presentation.pdf re:http://www.converter-radio.com/understandingSOA.pdf Dear Sir Author of this e-mail have some questions about ADC .EXcuse the author ,if questions are not relevant 1.Is it possible to develop today (from technology ,not hte market demand point of view ) 18 bit ADC, Fin 70 mhz ,BW= 20 mhz ,80-100 msps ,SFDR 100+ dBFS ,SNR 80+db by input -1 dbFS If powerd dissispated limited a. until 5 watt b until 50 watt 2. AN/ FPQ -6 C band Appolo radar http://en.wikipedia.org/wiki/AN/FPQ-6 have had Dynamic range in excess of 120 db , IF 30 mhz and BW until 2 mhz Is it possible to develop 20-24 bit ADC converter with atleast 10 msps Fin 30 mhz , SFDR 110-120 dbFS ,SNR 90 -100 dbfs Relevant comment would appreciated ##################################
milstar: From:"Brannon, Brad" Analog Device [Add] To: milstar Date:Mon, 16 Jan 2012 4:59 AM (5 hours 17 minutes ago) Show Raw MessageShow full header Sir Without an NDA in place, I am not at liberty to discuss much more. ############################################# NDA ? error - NSA ? (prim awtora postinga) I am sorry for the inconvenience. I will forward your requests to our converter marketing. Brad -----Original Message----- From milstar To: Brannon, Brad Subject: re3 -18 bit ADC, Fin 70 MHz ,20 MHz, 80-100 msps ,SFDR 100+ dBFS ,SNR 80+db by input -1 dbFS To Analog Device Mr. Brad Brannon Copy to GMR (DARPA NLEQ) Gil Raz Dear Sir Thank you for your answer You wrote 1 ... SNR in 20 MHz BW with a sample rate of about 125 MSPS can approach the mid-80s. this seems consistent with what you have asked. 2...I would say that right now to achieve consistent performance above 100 dB at 70 MHz would be less than 5 watts. Perhaps 2-3 is possible Witch kind of result be matched ,from technology perspective (without limitation of market demand ,expense and another questions ) ? if power consumated of one core ADC limited untill 50 watt and ADC can be cryogen cooled/example 1 kg belov) ? On 70 mhz ? For 20 mhz IF ,Input -1 db DBFS 60-100 msps 18-20 bit ? ,SNR more as 8x dbfs ? ,SFDR more as 1xx dbFS ? for ADC only ################################################################## 120 dbfs with NLEQ from DARPA ? Is it realistic ? For DARPA project ? EXcuse the author if questions are not relevant 3. As you knew -most broadly used PAW 70 mhz and 140 mhz http://www.triquint.com/products/types/filters/if/ http://www.triquint.com/products/types/filters/if/standard-70mhz-family.cfm http://www.triquint.com/products/types/filters/if/standard-140mhz-family.cfm 4. From M.Skolnik NRL Bandwitch for different radar mode For most of the function Fin/BW 70/200 mhz or 140/40 mhz For SAR/ISAR -strech processing Table 5.1 shows the range of parameters that can be observed as a function of radar mode. 5.12 MULTIFUNCTIONAL RADAR SYSTEMS FOR FIGHTER AIRCRAFT 1.Real beam map 0.5 -10 mgz 2.Doppler beam sharp 5-25 mgz 3. SAR 10 -500 mgz 4.A-S range 1-50 mgz 5.PVU 1-10 mgz 6.TF/TA 3-15 mgz 7.Sea surface search 0.2 -500 mgz 8.Inverse SAR 5-100 mgz 9. GMTI 0.5-15 mgz 10.Fixed target track 1-50 mgz 11.GMTT 0.5 -15 mgz 12.Sea Surface track 0.2-10 mgz 13.Hi power Jam 1-100 mgz 14.CAl/A.G.C 1-500 mgz 15A-S data link 0.5-250 mgz 6. Exist some Radar ,where can be accepted cryogen cooling of LNA ,Mixer ,IF and ADC a. All with average(!) power 1 megawatt -SBX, Don-2N, Cobra Dane and 250+ square metr appertura b. Some of radar as russian A-2500/S-300v4 have electrostatic amplifier ( can hold miltiple 100 watt on LNA input ) example of miniature cryogen cooling http://callisto-space.com/en/products/miniature-cryogenic-low-noise-amplifiers.html
milstar: definizii oversampling and undersampling ot razrabotchika http://www.edn.com/archives/1996/110796/23df_07.htm?text=brannon
milstar: smotri gl. 2.13 M.Skolnik ,Radar izdanie 2008 goda http://www.scribd.com/doc/49249408/0071485473-Radar-Handbook3rd 2.13 Dynamic Range and A/D convesion cosiderations
milstar: smotri M.Skolnik ,Radar izdanie 2008 goda 4.3 Dynamic Range and Stability requirement 4.24 ADC in Doppler radar http://www.scribd.com/doc/49249408/0071485473-Radar-Handbook3rd ...The most stressing dynamic range requirement is due to main beam clutter ,when searching for small low flying target ------------------------------------------- example 4.15 C/N 53 db na wisote RLS 1000 fut/300 metrow trebuetsja 12 bit dlja 63 db ------------------- 12 bit ENOB -eto 16 bitnie AZP ######################### 12 bit wisokoskorostnie AZP/ 1-3.6 GSPS / e2v,TI,National eto 9 bit ENOB
milstar: Statja Analog Device -averaging 32 ADC + 15 db in SNR http://www.analog.com/library/analogDialogue/archives/39-05/multichannel.pdf Lutschie 16 bit ADC segodnja dajut po 80 -81 db SNR na 70 mhz pri 80 -125 msps (TI ADS5481-83, LLTC LT2215-17,) i li 84 db na 10 mhz(TI) pri cene 40-70 $
milstar: http://www.ti.com/lit/ds/symlink/ads5482.pdf ADS5482 na 30 mhz(IF programmi Appolo AN/FPQ -6 http://en.wikipedia.org/wiki/AN/FPQ-6) SNR 80.7 dBFS SFDR -98 dbc SINAD-79.3 dbc pri 105 msps na 70 mhz SNR -80.1 dBFS SFDR -91 dbc /silno padaet) SINA-78.2 dbc ENOB na 30 mhz -12.88 bit ################### Konkurent Low noise LTC221 7105 msps http://cds.linear.com/docs/Datasheet/2217f.pdf 30 mhz SNR -81.1 dBFS SFDR -95 dbc ( pri 25°C) SINAD -81.1 70 mhz SNR -80.4 dBFS SFDR -92 dbc(25°C) SINAD -80
milstar: Esche odin maloschum AD9265 http://www.analog.com/en/analog-to-digital-converters/ad-converters/ad9265/products/product.html Wse 3 stojat menee 100$ za stuku T.e. wpolne mozno ispolzowat averaging 32 stuki na 70 mhz IF s 20 mhz polosoj teoreticheski SNR 80 + 15 dbc (is stati AD wische) Prakticheski werojatno meschne TI poluchilo + 4.8 db dlja 4 ADC experimentalno No s xoroschim chansom SFDR budet 93 + 10 db ot NLEQ/DARPA SNR bolee 90 dbc a okno pri strech processing w 5 raz wische chem y MMW /Lincoln po publichnim dannim /nawernjaka yze modernizirowan/= 20 mhz
milstar: ypominaetsja averaging 100 ADC s ylutschenime SNR 20 db High speed analog to digital converter basics http://www.ti.com/lit/an/slaa510/slaa510.pdf
milstar: http://www.mikron.sitronics.ru/products/micron/technology/ Технологии В «СИТРОНИКС Микроэлектроника» для разработки и производства микросхем используются следующие технологические процессы: БиКМОП SiGe • Проектная норма – 250 нм (2011 год) • Проектная норма – 180 нм (2012 год) • СВЧ и УВЧ до 10ГГц (АФАР, конвертеры и синтезаторы для радиолокационных систем и спутниковой связи) --------------------------- Dostatochno dlaj razrabotki Rossijskogo 16 bit AZP s 250 msps na Fin 300 mhz ,SFDR 90-95 dbFS ,SNR 73-76 dbc
milstar: http://homepage.fudan.edu.cn/mxcktccx/files/2011/09/16b125_JSSC912.pdf Statja Analog Device Fundamentalnaja zawisimost snizenie SNR na 3 db rawnoznahcno ymenscheniju potr. moschnosti w 2 raza ili snizeniju polosi signala w 2 raza
milstar: Wopros . - " ...Podozrewaju chto w RLS Irbis-E i Bars s wisokim chansom mnogo amerikanskix komplektujuschix ... ADC k primeru ... Pochemu wi ne xotite razrabotat rossijskie ADC ? . Wsja texnologija 0.18-0.35 microna w Rossii dawno est ..." Otwet -" ... Eto wopros k Rossijskomu prawitelstwu " -Sinani ,zam direktora po nauchnoj rabote NIIP ---------------------------------------------------------------------------------------------------------------------- (NIIP -razrabotchik Bars,Irbis,Buk-2) www.niip.ru
milstar: Rossijskij 14 bit 20 msps ADC http://multicore.ru/index.php?id=652&utm_source=adcmcmain&utm_medium=cpc&utm_campaign=ChipExpo2009
milstar: http://www.imeko.org/publications/tc4-2002/IMEKO-TC4-2002-042.pdf ADC DYNAMIC RANGE IMPROVEMENT FOR WIDEBAND HF RECEIVERS T.H.Pearce BAE Systems, Australia FEEDFORWARD ARCHITECTURE The two-stage RF feedforward arrangement shown in Figure 2 offers a possible means of achieving the desired improvement in dynamic range, and linearity, by operating two ADC’s in cascade. The technique has been applied to extending the dynamic range and linearity of two third order continuous time bandpass sigma-delta ADC’s for use in narrowband HF radar receivers [6]. It is similar in principle to the two-pass technique frequently adopted in Nyquist sampled monolithic ADC’s, except the error signal is returned to continuous time form, by means of a low pass filter, before application to the second stage, obviating the need for a sample and hold at the input.
milstar: Wideband Digital Receiver/Digitizer Module VPX-1151 http://ww1.prweb.com/prfiles/2011/09/29/4747754/VPX-1151.pdf Product Overview The VPX-1151 is an ultra high-speed digitizer and processing solution that enables direct RF-to-Digital conversion between 100 MHz and 3 GHz. SIGINT (COMINT/ELINT) • Joint Airborne SIGINT Architecture (JASA) IF Digitizer/processor • RADAR • Satellite Receiver
milstar: HIGH PERFORMANCE, 16-BIT, 250 MSPS WIDEBAND RECEIVER WITH ANTIALIASING FILTER (CN0227) http://www.analog.com/en/circuits-from-the-lab/CN0227/vc.html http://www.analog.com/static/imported-files/circuit_notes/CN0227.pdf
milstar: AF202 Dual Channel 12-bit 1.5 GSPS ADC FMC http://www.go2aes.com/Embedded/DataSheets/apissys/ApisSysAF202DataSheet.pdf http://www.apissys.com/html/adc.php
milstar: - В России уже несколько лет реализуются меры по развитию отечественной электронной компонентной базы. Как ваш концерн участвует в этой работе? - Абсолютно точно понятно, что это серьезная, национальная проблема. В сфере микроэлектроники мы ввели в Зеленограде линию по производству микросхем технологии сначала 180 нанометров, потом 90 нанометров, решаем вопрос о переходе на 65 нанометров - это серьезный шаг вперед. --------------- Генеральный директор ОАО "РТИ" Сергей Боев http://novosti-kosmonavtiki.ru/forum/forum12/topic3035/?PAGEN_1=7 Eto dostatochno dlja sozdaniya Rossijskix AZP - 12 bitnix 1gsps , 16 bitnix s 250 msps Neobxodimo razvitie topologii ... ----------------------------------- Когда мы говорим об использовании импортной электронно-компонентной базы в наших изделиях, то приходится признать, что она имеется в наших изделиях. Иногда их доля значительно выше 50 процентов. Например, в космической отрасли она зашкаливает за 90 процентов. Хотя, как вы понимаете, для той области, которой мы занимаемся, для оборонной отрасли и военного космоса это архиважная задача. Очень большие средства тратятся и много сил отвлекается на проверку зарубежной электронной компонентной базы. Особенно класса space и military.
milstar: • 100 MHz, 16-bit IF sampling improving sensitivity and dynamic range in 5 independent channels http://wakenet.eu/fileadmin/user_upload/2nd_workshop/presentations/021-Drake.pdf
milstar: http://jocoleman.info/pubs/papers/SkolnikCh25.pdf
milstar: http://ntms.org/eme/presentations/w5lua/K5SDR-EME%20Conference%202010.pdf
milstar: http://prod.sandia.gov/techlib/access-control.cgi/2002/022127.pdf http://www.pentek.com/tutorials/19_2/Radar.cfm
milstar: http://www.converter-radio.com/radio101.pdf
milstar: Быстродействующий 8-разрядный АЦП http://www.russianelectronics.ru/developer-r/review/intergal/354/doc/835/ Микросхема преобразователя разработана на основе КМОП-технологии с проектными нормами 0,18 мкм. Опытная партия была изготовлена на фабрике SilTerra. Быстродействующие АЦП соответствуют лучшим мировым показателям для этого уровня технологии. Структурная схема преобразователя показана на рисунке 1. В его состав входят два АЦП параллельного типа с частотой преобразования 200 МГц каждый. Оба блока работают параллельно-поочередно. Схема синхронизации обеспечивает равные временные интервалы между опросами АЦП, а результирующая частота опроса вдвое больше частоты отдельных блоков АЦП. Вследствие технологического разброса параметров невозможно достичь полной идентичности блоков. В результате статические параметры всей микросхемы могли бы оказаться значительно хуже параметров входящих в нее блоков. Элементом ноу-хау стал алгоритм цифровой обработки сигналов двух и более преобразователей, который выполняет нормирование и интерполяцию сигналов, выделение перепадов входного сигнала и коррекцию ошибок, возникающих под воздействием импульсных помех. Приоритетное выделение перепадов входного сигнала расширяет полосу преобразуемого входного сигнала до 400 МГц. Это свойство дает возможность оцифровать радиосигнал с одновременным переносом его частоты в низкочастотный диапазон. Серьезной проблемой применения АЦП параллельного типа является их большая входная емкость (20ѕ40 пФ), которая возникает при подключении к входной цепи 255 компараторов. Входная емкость ухудшает параметры источника сигнала и влечет увеличение энергопотребления. Однако в новом быстродействующем преобразователе удалось снизить входную емкость до 5 пФ. Это достигнуто за счет применения субмикронных транзисторов, предварительных усилителей и схемы аналоговой интерполяции. Число усилителей значительно меньше числа компараторов, что сокращает входную емкость в несколько раз. Поток выходных данных со скоростью 400 Мбайт/с выводится через скоростные порты с уровнями LVDS. Технологический процесс изготовления АЦП характеризуется возможностью использования КМОП-транзисторов с напряжением питания 3,3 В (0,35 мкм) и 1,8 В (0,18 мкм). В структуре микросхемы реализуется: – полная изоляция от подложки как n-канальных, так и p-канальных МОП-транзисторов; – система металлизированных соединений с 6 уровнями проводников; – конденсаторы большой емкости со структурой МДП; – поликремневые резисторы с различным слоевым сопротивлением. Размер кристалла АЦП — 3,2 x 2,0 мм, потребляемая мощность — 450 мВт, питание — от одного источника 3,3 В. Кристалл устанавливается в 48-контактный безвыводный корпус на металлокерамическом носителе типа CLCC-48. Помимо этой микросхемы, в «Юник Ай Сиз» разработан ряд блоков АЦП, которые используются в других проектах компании. Среди них: – 10-разрядный АЦП, 40 Мвыб./с, 150 мВт; – 16-разрядный АЦП, 200 Квыб./с, 30 мВт; – 8-разрядный АЦП, 100 Квыб./с, 3 мВт. В настоящее время компания ведет разработку специализированной микросхемы 10-канального АЦП по заказу российского предприятия. Оцените материал: 012345 Автор: Денис Адамов, к.т.н., Артур Сибагатуллин
milstar: Summary High-speed RF signal capture with wide dynamic range signals is readily achievable with today's high-speed ADCs. With careful design followed by the appropriate digital sig- nal processing, it is possible to capture and recreate signals with dynamic ranges in excess of 100 dB. http://highfrequencyelectronics.com/Archives/Sep08/HFE0908_S_Crean.pdf Symtx Inc. has implemented a dual ADC scheme to increase digitizer dynamic range as shown in Figure 3. The design uses a high-gain channel to process low-level sig- nals and a low-gain channel to process high-level signals, with simultaneous sampling of both channels in parallel. The gain difference between the high-level and low level ADCs is compensated with an appropriate n-bit left shift to give the correct scaling. A DSP after the two ADCs then selects the correct ADC output, adjusts for gain, and merges the two to create a 20-bit word with the desired dynamic range.
milstar: DYNAMIC RANGE REQUIREMENTS The demands of an ADC capable of accommodating the entire HF spectrum without distortion are quite formidable. The converter must be capable of accommodating many high level signals simultaneously, particularly those from high power HF broadcast station carriers. These can each produce in the region of –30 dBm at the receiver input, even with spectral shaping in the antenna matching network to offset the variation of external noise with frequency. The total signal power can easily be 20 dB higher at –10 dBm, and a further 10 dB allowance for occasional peaks leads to a maximum in the region of 0 dBm. Automatic Gain Control (AGC) in the form of a variable attenuator ahead of the ADC is also generally necessary to accommodate an inevitable variation with propagation conditions [3, 4]. The noise floor of the converter must be low enough to provide a noise figure for the receiver of better than 12 dB for communications purposes and closer to 6 dB at the higher frequencies for HF radar [5]. This translates to a spurious free dynamic range (SFDR) requirement of 127 dB in a 3 kHz resolution bandwidth, and a signal to noise spectral density ratio of at least 162 dBc/Hz, increasing to 168 dBc/Hz for HF radar. http://www.imeko.org/publications/tc4-2002/IMEKO-TC4-2002-042.pdf
milstar: http://www.tekmicro.com/products/product.cfm?id=83&gid=6
milstar: MIT Lincoln Laboratory developed the technology for an all-digital radar receiver for airborne surveillance array radar like that of the UHF E-2C.43 They are A/D sampling directly at UHF (~430 MHz) using a Rockwell 8-bit, 3 Gbps A/D running at room temperature. Three stages of down conversion are done digitally and because the A/D quantization noise is filtered, the effective number of bits of the A/D is increased. For example, if the signal bandwidth is only 5 MHz, the increase in signal-to-noise ratio is 3 GHz/2 (5 MHz) = 25 dB, so the increase in the number of effective bits is 25 dB divided by 6 dB/bit or 4.2 bits to yield 12 bits total. The whole digital receiver is on an 8" by 8" card that uses three 0.6 mm chips. In the future these three chips could be replaced by a single 0.35 mm CMOS chip. http://www.uspoliticsonline.net/science-technology/25952-aesa-technology-next-generation-radar-2.html
milstar: http://www.apissys.com/pdf/AF202.pdf
milstar: http://www.imeko.org/publications/tc4-2002/IMEKO-TC4-2002-042.pdf
milstar: http://www.dtic.mil/cgi-bin/GetTRDoc?AD=ADA391707 NRL
milstar: CONCLUSIONS The performance realized with the experimental Stacked ADC described in this report has demonstrated the feasibility of increasing the effective dynamic range in a practical radar signal processor from 60 to 65 dB to 78 to 83 dB while maintaining a SINAD of 45 to 50 dB against a two-tone input signal.
milstar: http://www.flex-radio.com/FLEX-6000.pdf
milstar: The Advance e710 board weighs just under 150grams yet delivers 75GFLOPS/s (dgemm performance) or 18GFLOPS/s (FFT performance), so it is easy to see why the CSX700 is an ideal platform for high performance processing applications that require small size, weight and power footprints http://www.clearspeed.com/products/csx700embedded.php
milstar: Synthetic Aperture Radar - SAR -------------------------------------------------------------------------------- We excel in processing Radar data sets, from front end capture and pulse compression techniques to SAR processing and beyond. The ClearSpeed processor platform efficiently computes single precision complex FFTs (see our CSX700 FFT benchmarks). By being software programmable the developer can instruct the processor to perform additional operations while the data is distributed across the processing array. http://www.clearspeed.com/applications/syntheticapertureradar/index.php http://www.clearspeed.com/applications/digitalsignalprocessing/csx700fftperformance.php
milstar: 2/4-Channel 250MSPS 16-bit PCIe A/D Board Achieves > 160dB Dynamic Range with on-board Hardware Averaging ######################################## http://www.ultraviewcorp.com/displaynews.php?news_id=9
milstar: http://www.analog.com/static/imported-files/circuit_notes/CN0268.pdf
milstar: http://www.embedded.com/design/analog/4373038/2/Product-How-To--Passive-filter-options-achieve-very-high-SNR--SFDR-in-a-low-power-16-bit-ADC-interface--Part-1-
milstar: http://www.youtube.com/watch?v=0JFU4oFmAdE
milstar: http://www.youtube.com/watch?v=0JFU4oFmAdE
milstar: http://electronicdesign.com/analog/dither-can-boost-sampled-data-system-performance-least-10-db
milstar: - В России уже несколько лет реализуются меры по развитию отечественной электронной компонентной базы. Как ваш концерн участвует в этой работе? - Абсолютно точно понятно, что это серьезная, национальная проблема. В сфере микроэлектроники мы ввели в Зеленограде линию по производству микросхем технологии сначала 180 нанометров, потом 90 нанометров, решаем вопрос о переходе на 65 нанометров - это серьезный шаг вперед. Когда мы говорим об использовании импортной электронно-компонентной базы в наших изделиях, то приходится признать, что она имеется в наших изделиях. Иногда их доля значительно выше 50 процентов. Например, в космической отрасли она зашкаливает за 90 процентов. Хотя, как вы понимаете, для той области, которой мы занимаемся, для оборонной отрасли и военного космоса это архиважная задача. Очень большие средства тратятся и много сил отвлекается на проверку зарубежной электронной компонентной базы. Особенно класса space и military. - То есть вы не согласны с теми, кто говорит, что чипы можно купить и за рубежом, никакой беды в этом нет? - Это абсолютно не правильно. Конечно, мы вынуждены будем покупать микросхемы за рубежом, но при этом надо помнить, что наличие собственной микроэлектроники - это вопрос обеспечения национальной безопасности. Это связано напрямую с возрастающей ролью информационных технологий и необходимостью обеспечения кибербезопасности во всех сферах жизни общества. Генеральный директор ОАО "РТИ" Сергей Боев: http://www.militarynews.ru/excl.asp?ex=152
milstar: TECHNICAL ABSTRACT (Limit 2000 characters, approximately 200 words) Ridgetop Group will develop a 3X improvement in sampling resolution over current state-of-the art analog-to-digital converter (ADC) technology to support reconfigurable/reprogrammable communication systems. The significance of this innovation lies in the time-interleaved pipeline ADC, based on the most advanced silicon-germanium (SiGe) BiCMOS technology available, with over 2 bits higher effective number of bits (ENOB = 11.0 bits) than the best commercially available radiation-tolerant 2 GS/s ADCs (ENOB = 8.9 bits). In addition, the ADC consumes 65% less power than commercial ADCs, conserving valuable spacecraft power. For maximum flexibility and minimal power consumption, the ADC provides two configurable pipeline channels and four programmable operation modes. The ADC will also provide 3 GHz input analog bandwidth for direct sampling of RF signals in the S-band. The ADC will tolerate 5 Mrads of total ionizing dose (TID) radiation due to the inherent radiation tolerance of the SiGe heterojunction bipolar transistors (HBT), 130 nm thin-oxide CMOS transistors, and standard radiation-hardening-by-design (RHBD) techniques. The ADC will be also sufficiently hardened against single-event effects (SEE). Ridgetop will fabricate and test the ADC in the IBM 130 nm BiCMOS SiGe process in Phase 2 of this SBIR program. http://sbir.gsfc.nasa.gov/SBIR/abstracts/11/sbir/phase1/SBIR-11-1-O1.02-9553.html
milstar: http://www.analog.com/static/imported-files/circuit_notes/CN0227.pdf The overall circuit has a bandwidth of 152 MHz with a pass band flatness of 1 dB. The SNR and SFDR measured with a 120 MHz analog input are 72.6 dBFS and 82.2 dBc, respectively.
milstar: The ADC input bandwidth and distortion performance must be adequate at the IF frequency, rather than only baseband. This presents a problem for most ADCs designed to only process signals in the first Nyquist zone—an ADC suitable for undersampling applications must maintain dynamic performance into the higher order Nyquist zones. http://www.analog.com/static/imported-files/tutorials/MT-002.pdf Sampling signals above the first Nyquist zone has become popular in communications, because the process is equivalent to analog demodulation. It is becoming common practice to sample IF signals directly and then use digital techniques to process the signal, thereby eliminating the need for an IF demodulator and filters.
milstar: igure 3: Quantization Noise Spectrum Showing Process Gain The significance of process gain can be seen from the following example. In many digital basestations or other wideband receivers the signal bandwidth is composed of many individual channels, and a single ADC is used to digitize the entire bandwidth. For instance, the analog cellular radio system (AMPS) in the U.S. consists of 416 30-kHz wide channels, occupying a bandwidth of approximately 12.5 MHz. Assume a 65-MSPS sampling frequency, and that digital filtering is used to separate the individual 30-kHz channels. The process gain due to oversampling for these conditions is given by: Process Gain =10log10 fs =10log10 65×106 2⋅BW 2×30×103 = 30.3dB. Eq. 11 The process gain is added to the ADC SNR specification to yield the SNR in the 30-kHz bandwidth. In the above example, if the ADC SNR specification is 65 dB (dc to fs/2), then it is increased to 95.3 dB in the 30-kHz channel bandwidth (after appropriate digital filtering).
milstar: SNR, PROCESS GAIN, AND FFT NOISE FLOOR RELATIONSHIPS Figure 6 shows the FFT output for an ideal 12-bit ADC. Note that the average value of the noise floor of the FFT is approximately 107 dB below full-scale, but the theoretical SNR of a 12-bit ADC is 74 dB. The FFT noise floor is not the SNR of the ADC, because the FFT acts like an analog spectrum analyzer with a bandwidth of fs/M, where M is the number of points in the FFT. The theoretical FFT noise floor is therefore 10log10(M/2) dB below the quantization noise floor due to the processing gain of the FFT. In the case of an ideal 12-bit ADC with an SNR of 74 dB, a 4096-point FFT would result in a processing gain of 10log10(4096/2) = 33 dB, thereby resulting in an overall FFT noise floor of 74 + 33 = 107 dBc. In fact, the FFT noise floor can be reduced even further by going to larger and larger FFTs; just as an analog spectrum analyzer's noise floor can be reduced by narrowing the bandwidth
milstar: Practical Examples A high-speed 12-bit converter developed by e2v, the EV12AS200, comprises a single-core 1.5-Gsample/s ADC with 2.3-GHz bandwidth.3 It’s based on a 200-GHz silicon-germanium-carbon (SiGeC) bipolar technology. In L-Band radar applications, the device enables direct digitizion of 500-MHz broadband arbitrary waveforms in the second Nyquist region closer to the antenna—a key factor when designing flexible, simplified radar receiver systems. Adding dither to the EV12AS200’s input signal will enhance performance. This was demonstrated in a test using a filtered noise diode as the dither source input to one side of the ADC’s differential input (Fig. 3). http://electronicdesign.com/analog/dither-can-boost-sampled-data-system-performance-least-10-db
milstar: http://www.eetimes.com/design/microwave-rf-design/4370321/Selecting-high-speed-ADCs-for-high-frequency-applications?pageNumber=1
milstar: Сверхбыстродействующие АЦП и ЦАП компании E2V http://www.symmetron.ru/suppliers/e2v/dac.shtml
milstar: http://www.vaisala.com/en/defense/products/weatherradar/Pages/RVP900.aspx The RVP900™ Sigmet Digital Receiver and Signal Processor provides comprehensive digital IF and signal processing functions on an open Linux PC platform 100 MHz, 16-bit IF sampling improving sensitivity and dynamic range in 5 independent channels 38.4 Billion multiply accumulates cycles per second which is a x5 increase over the RVP8™ RVP900™ Sigmet is compatible with any PC server using a Ethernet interface. The next generation hardware is the next faster PC chip. Independent and parallel FIR filtering allowing dual pulse width and dual frequency strategies on each receive channel Dual Polarization, Wide Dynamic Range, and Pulse Compression ready http://www.vaisala.com/en/defense/products/weatherradar/Pages/RVP900.aspx
milstar: 12 bit 800 msps http://www.ti.com/lit/ds/symlink/ads5401.pdf
milstar: http://www.eetimes.com/document.asp?doc_id=1316160 Key highlights: Slashes board space: 12-mm by 12-mm footprint reduces board space by 80 percent over current devices, enabling the use of wideband ADCs in applications where they would not have fit previously, such as small form factor remote radio units. Increases performance-to-power ratio: Provides 2-dB higher SNR and 10-dBc higher SFDR than existing solutions at speeds up to 900 MSPS while reducing power up to 20 percent. Simplifies system design: Optional 2x decimation filter eases analog filter requirements and reduces the data interface rate by half. Enables linear and efficient wideband transmit: Provides power amplifier linearization bandwidths up to 900 MHz for fifth order digital pre-distortion of a 180-MHz transmit signal. Pin-compatible, export-compliant family Also new to the market, the complementary 12-bit ADS54T02 family includes three 1- and 2-channel, 500- to 750-MSPS dual-mode feedback and receiver ICs for time division duplex (TDD) base stations. The devices are pin-compatible with the ADS5409 family. Package, availability and pricing The 12-bit ADS5409 family includes the following devices, most which are available today in a 12-mm by 12-mm BGA package: ADS5401: 1 channel at 800 MSPS for US$187.50 ADS5403: 1 channel at 500 MSPS for US$125.00 ADS5404: 2 channel at 500 MSPS for US$218.75 ADS5407*: 2 channel at 500 MSPS for US$239.95 ADS5402: 2 channel at 800 MSPS for US$349.65 ADS5409: 2 channel at 900 MSPS for US$393.35; will be available in June 2013 The 12-bit ADS54T02 family is also available today and includes the following devices in a 12-mm by 12-mm BGA package: ADS54T01: 1 channel at 750 MSPS for US$187.50 ADS54T04: 2 channel at 500 MSPS for US$349.65 ADS54T02: 2 channel at 750 MSPS for US$218.75 All prices quoted are for 1,000-unit quantities.
milstar: http://cds.linear.com/docs/en/datasheet/2217f.pdf Sample Rate: 105Msps ■ 81.3dBFS Noise Floor ■ 100dB SFDR ■ SFDR >90dB at 70MHz ■ 85fsRMS Jitter ■ 2.75VP-P Input Range ■ 400MHz Full Power Bandwidth S/H ■ Optional Internal Dither ■ Optional Data Output Randomizer ■ LVDS or CMOS Outputs ■ Single 3.3V Supply ■ Power Dissipation: 1.19W ■ Clock Duty Cycle Stabilizer ■ Pin Compatible with LTC2208 ■ 64-Pin (9mm × 9mm) QFN Package APPLICATIONS ■ Telecommunications ■ Receivers ■ Cellular Base Stations ■ Spectrum Analysis ■ Imaging Systems ■ ATE
milstar: На создание высокоточного оружия выделят 8 млрд рублей Комментарии 5 Столичный завод «Пульсар» и еще три предприятия, выпускающие электронные компоненты для радиолокации и систем наведения, объединят в кластер На создание высокоточного оружия выделят 8 млрд рублей Фото: gz-pulsar.ru Объединение четырех предприятий, выпускающих электронные компоненты для радиолокации и систем наведения, должно обеспечить новой элементной базой российское высокоточное оружие. Холдинг «Росэлектроника» («дочка» госкорпорации «Ростех») создает кластер на базе московского предприятия «Пульсар». — Предстоит серьезная модернизация, внедряемые технологии позволят заглянуть в новый этап развития вооружений. За пять лет в новую площадку инвестируют 8–10 млрд рублей, 70% из них — бюджетные средства, кроме того, будем инвестировать прибыль, использовать кредиты и лизинг, — сообщил «Известиям» гендиректор ОАО «Государственный завод «Пульсар» Валерий Буробин. По его словам, это беспрецедентная сумма — за последние 10 лет «Пульсар» получил всего порядка 150 млн рублей. Гендиректор «Росэлектроники» Андрей Зверев подтвердил, что вложения уже утверждены. — На модернизацию технологических линий создаваемого кластера планируем инвестировать порядка 8 млрд рублей, — рассказал глава компании. К «Пульсару» присоединят три столичных ОАО: «Оптрон», Особое конструкторское бюро МЭЛЗ и Центральное конструкторское бюро специальных радиоматериалов. Переезд уже начался. Объединение должно завершиться за три года. — Мы должны запустить производство в конце 2016 года. Сроки жесткие, потому что в 2020-х годах новое вооружение должно поступить в войска, — подчеркнул Буробин. Изготовленные на «Пульсаре» транзисторы используются в авиационных радарах (в частности в истребителе Т-50 — его серийное производство должно начаться в 2015 году), в радиолокационных комплексах «Небо-М», «Сопка», наземной станции дальнего обнаружения «Воронеж-ДМ», частично в комплексах «Панцирь» и «Искандер». — Это разные виды вооружений, но там используются те же транзисторы, — отметил Валерий Буробин. Кластер «Пульсар» должен будет внести вклад в развитие отечественного высокоточного оружия — управляемых ракет и авиационных бомб, зенитно-ракетных комплексов нового поколения и др. На заседании Совета безопасности летом прошлого года президент России Владимир Путин отметил, что «необходимо адекватно реагировать на развитие высокоточного оружия в мире». Оружие с высокой вероятностью поражения цели появилось во второй половине XX века. Боеприпасы и ракеты стали оснащаться инерциальными датчиками, уменьшающими отклонения от траектории, радио- и лазерной «подсветкой» цели, автоматическими системами наведения. Сегодня это направление развития вооружения считает одним из наиболее перспективных. В 2012 Минобороны обещало, что российские военно-воздушные силы до 2020 года увеличат количество высокоточного оружия в 18 раз. Экс-начальник вооружения Минобороны России генерал-полковник Анатолий Ситнов полагает, что одного только технического переоснащения предприятий недостаточно. — Надо развивать научные школы, а не объединять предприятия. Новую технологию технологию нам никто не даст, мы можем купить только станки. Надо заботится об укреплении и создании прорывных научных школ, давать гранты молодым специалистам, — считает Ситнов. При этом эксперт отметил, что отечественная сверхвысокочастотная электроника остается на высоком уровне, в отличие от микроэлектроники, отставание в которой существенно. — Советский Союз и Россия были всегда впереди по СВЧ, мы были на нормальном уровне и хорошо развивались, — заявил Ситнов. Читайте далее: http://izvestia.ru/news/565380#ixzz2sv0LUZCP
milstar: LTC2107 - 16-Bit, 210Msps High Performance ADC Features 98dBFS SFDR 80dBFS SNR Noise Floor Aperture Jitter = 45fsRMS PGA Front-End 2.4VP-P or 1.6VP-P Input Range Optional Internal Dither Optional Data Output Randomizer Power Dissipation: 1280mW Shutdown Mode Serial SPI Port for Configuration Clock Duty Cycle Stabilizer 48-Lead (7mm × 7mm) QFN Package This Product is subject to United States Export Control and may require a license for export to certain countries --------------------- http://www.linear.com/product/LTC2107
milstar: http://cds.linear.com/docs/en/datasheet/2107f.pdf AC performance includes, SNR = 80dBFS, SFDR = 98dBFS. Aperture jitter = 45fsRMS allows direct sampling of IF frequencies up to 500MHz with excellent performance. Features such as internal dither, a PGA front-end and digital output randomization help maximize performance. Modes of operation can be controlled through a 3-wire serial interface (SPI). The double data rate (DDR) low voltage differential (LVDS) digital outputs help reduce digital line count and enable space saving designs.
milstar: AD9625 http://www.analog.com/static/imported-files/data_sheets/AD9625.pdf http://videos.analog.com/video/3255267136001/Using-the-AD9625-25-GSPS-High-Speed-AD-Converter/
milstar: http://www.ti.com/lit/ds/symlink/adc12j4000.pdf
milstar: The AD9680 is a dual, 14-bit, 1 GSPS analog-to-digital converter (ADC). The device has an on-chip buffer and sample- and-hold circuit designed for low power, small size, and ease of use. This device is designed for sampling wide bandwidth analog signals of up to 2 GHz. The AD9680 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package. The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. http://www.analog.com/static/imported-files/data_sheets/AD9680.pdf
milstar: В таблице 2 приведены основные виды электровакуумных СВЧ приборов и устройств, имеющие мировой и российский приоритет, технические и технологические решения которых защищены патентами Российской Федерации. По совокупности своих технических и эксплуатационных характеристик эти приборы являются лучшими в своих классах и определяют мировой технический уровень. В таблице приведены области применения этих СВЧ приборов, лидирующие предприятия-разработчики и изготовители, а также представлены применяемые для этих же целей приборы за рубежом и их изготовители. http://www.hse.ru/data/2013/02/12/1308493137/СПИ%20ТП%20СВЧ%20технологии%2025%2012%202012.pdf СТРАТЕГИЧЕСКАЯ ПРОГРАММА ИССЛЕДОВАНИЙ технологической платформы «СВЧ технологии» Утверждена 17 декабря 2012 года на заседании Наблюдательного совета технологической платформы «СВЧ технологии» под председательством А.С. Якунина Директора Департамента радиоэлектронной промышленности Министерства промышленности и торговли Российской Федерации Основными потребителями СВЧ приборов и устройств являются предприятия ОПК радиоэлектронного профиля, разрабатывающие и серийно выпускающие радиоэлектронную аппаратуру прежде всего военного и, наряду с ней, аппаратуру двойного и (или) гражданского назначения. Наиболее крупными из них, формирующими рынок радиоэлектронной военной продукции являются предприятия, входящие в ОАО «Концерн ПВО «Алмаз-Антей» (ОАО ГСКБ «Алмаз-Антей» (Москва), ОАО «НИИ приборостроения им. В.В.Тихомирова» (Жуковский Московской обл.), ФГУП «ГРПЗ» (Рязань), ОАО «НИИ «Стрела» (Тула), ОАО МНИИ «Альтаир», ОАО «ВНИИРТ» (Москва), ОАО «ННИИРТ» (Нижний Новгород), а также ОАО «КБП» (Тула), ОАО «КБМ» (Коломна Московской обл.), ОАО «ЦКБА» (Омск), ФГУП «КНИРТИ» (Жуков Калужской обл.), ОАО «Корпорация «Тактической ракетной вооружение», ОАО ГосМКБ «Вымпел», ОАО ГосМКБ «Факел», ОАО «Российские космические системы», ФГУП «ЦНИИ «Комета» (Москва) и др. Разрабатываемые и выпускаемые ими системы радиоэлектронного вооружения на период до 2020 года будут в основном определять загруженность предприятий ОПК, в том числе и СВЧ подотрасли. Только по номенклатуре ФГУП «НПП «Исток» (Фрязино Московской обл.), разрабатывающему и серийно выпускающему СВЧ приборы и устройства для более 100 образцов современного и перспективного вооружения, объемы производства к 2017-2018 гг. планируется увеличить: по кристальному производству транзисторов и МИС СВЧ в 26 раз; по производству модулей СВЧ, в том числе для АФАР в 12 раз; по электровакуумным СВЧ приборам и КИ СВЧ в 2,3 раза; по радиоэлектронным устройствам в 4 раза.
milstar: he ADC12J4000 device is a wideband sampling and digital tuning device. Texas Instruments' giga-sample analog-to-digital converter (ADC) technology enables a large block of frequency spectrum to be sampled directly at RF. ADC12J400012-Bit 4GSPSADCWithIntegratedDDC The ADC12J4000 device is a wideband sampling and digital tuning device. Texas Instruments' giga-sample analog-to-digital converter (ADC) technology enables a large block of frequency spectrum to be sampled directly at RF. Excellent Noise and Linearity up to and beyond FIN=3GHz • Configurable DDC • Decimation Factors from 4 to 32 (Complex Baseband Out) • Usable Output Bandwidth of 800 MHz at 4x Decimation and 4000 MSPS • Usable Output Bandwidth of 100 MHz at 32x Decimation and 4000 MSPS • Bypass Mode for Full Nyquist Output Bandwidth • Low Pin-Count JESD204B Subclass 1 Interface • Automatically Optimized Output Lane Count • Embedded Low Latency Signal Range Indication • Low Power Consumption • Key Specifications – Max Sampling Rate: 4000 MSPS – Min Sampling Rate: 1000 MSPS – DDC Output Word Size: 15-Bit Complex (30 bits total) – Bypass Output Word Size: 12-Bit Offset Binary – Noise Floor: −149 dBFS/Hz or −150.8 dBm/Hz – IMD3:−64dBc(FIN =2140MHz±30MHzat −13 dBFS) – FPBW (–3 dB): 3.2 GHz – Peak NPR: 46 dB – Supply Voltages: 1.9 V and 1.2 V – Power Consumption – Bypass (4000 MSPS): 2 W http://www.ti.com/lit/ds/symlink/adc12j4000.pdf
milstar: http://www.analog.com/static/imported-files/tech_articles/GSPS-Data-Converters-to-the-Rescue-MS-2708.pdf AD9265, AD9680 1.25-2.5 GSPS 14 bit(!) ANALOG DEVICES UNVEILS NEW CLASS OF DATA CONVERTERS THAT SET 14-BIT, GSPS PERFORMANCE STANDARD Breakthrough performance, bandwidth, integrated functionality drive applications to direct RF sampling Norwood, MA (05/13/2014) - Analog Devices, Inc. (NASDAQ: ADI), the world’s data converter market share leader*, announced today the immediate availability of the dual-channel, 1.25-V,14-bit, 1-GSPS AD9680 A/D converter featuring the best noise and dynamic range performance in its class enabling the trend for direct RF sampling in communications, instrumentation and military/aerospace applications. Its noise density of -154 dBFs/Hz is the lowest in the industry. The breakthrough performance, bandwidth and integrated functionality of ADI’s wideband RF data acquisition technology allows for better signal extraction in congested RF environments over a wider bandwidth than ever before. The AD9680 is interoperable with FPGAs from majormanufacturers and supported with known good configurations. . The AD9680 combined with the recently announced 12-bit, 2-GSPS AD9625 A/D converter, demonstrate ADI’s innovation in providing leading edge offerings driving the trend toward direct RF sampling. http://www.analog.com/en/analog-to-digital-converters/high-speed-ad-converters/ad9680/products/05_13_14_ADI_Unveils_New_Class_of_Data_Converters/press.html 
milstar: http://www.e2v.com/content/uploads/2014/09/EV12AS200-Application-Note.pdf Implementing the EV12AS200 Application Note
milstar: http://www.analog.com/static/imported-files/data_sheets/AD9625.pdf 12 bit 2.5 GSPS
milstar: http://www.analog.com/static/imported-files/tech_articles/Maximizing-the-Dynamic-Range-of-Software-Defined-Radio-MS-2735.pdf Maximizing the Dynamic Range of Software-Defined Radio by Bob Clarke, systems applications engineering manager, and Kevin Kreitzer, field applications manager, Analog Devices, Inc.
milstar: ADC ARCHITECTURE The architecture of the AD9680 consists of an input buffered pipelined ADC. ################ The input buffer is designed to provide a termination impedance to the analog input signal. This termination impedance can be changed using the SPI to meet the termination needs of the driver/amplifier. The default termination value is set to 400 Ω. The equivalent circuit diagram of the analog input termination is shown in Figure 55. The input buffer is optimized for high linearity, low noise, and low power. http://www.analog.com/static/imported-files/data_sheets/AD9680.pdf THEORY OF OPERATION The AD9680 has two analog input channels and four JESD204B output lane pairs. The ADC is designed to sample wide bandwidth analog signals of up to 2 GHz. The AD9680 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package. The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations
milstar: http://www.analog.com/ru/analog-to-digital-converters/high-speed-ad-converters/ad9680/products/product.html oglavlenie na russkom ad9680 2*14 bit konvejernij pri f in 985 mhz ,1 GSPS SNR -60.5 dBFS SINAD -61.1 dBFS ENOB -9.8 bit SFDR -80 dBFS worst 2or 3 harmonic -80 dBFS Full power BW -2ghz
milstar: Choosing an ADC is a discussion in and of itself. The dynamic range of the ADC determines the systems architecture, and vice versa. So how much dynamic range is enough? The highest performance software-defined radios (and RF lab instruments) typically use 14-bit to 16-bit, high speed ADCs to sample at as high a frequency as possible for signals as wide as 250 MHz. For testing the widest signals in standards such as the alphabet soup that is 802.11, the industry preference is to use dual high speed ADCs such as the 14-bit AD9680 for quadrature sampling of I/Q signals at baseband with I/Q bandwidths of 500 MHz or more. Some applications need less dynamic range and will typically use a 12-bit GSPS ADC such as the AD9625 to grab a 500 MHz wide chunk of spectrum and bring it down to baseband using an integrated digital downconverter. The dynamic range of the ADC is the fundamental trade-off between analog and digital filtering. More analog filtering reduces the amplitudes of the interferers and the required range of the ADC, which must digitize both the desired signal and interferers to maintain a linear system. Analog filters, however, are nonideal and can exhibit group delay and phase. At the systems level, lots of filtering in the analog domain also means lots of potentially expensive mechanical shielding to maintain the filter’s isolation as well as the possibility of cascading multiple filters at multiple IFs to minimize leakage around the filters. In contrast, digital filters can have great shape factors, no leakage, and near ideal characteristics, but require increasing the ADC’s dynamic range to accommodate both the signal and interferers. http://www.analog.com/static/imported-files/tech_articles/Maximizing-the-Dynamic-Range-of-Software-Defined-Radio-MS-2735.pdf
milstar: Improvements for Air-Surveillance Radar Merrill Skolnik Systems Directorate Naval Research Laboratory Washington, D. C. 20375 http://dasl.mem.drexel.edu/Hing/Improvements%20for%20Air-surveillance%20radar.pdf L band, from 1215 to 1400 MHz, has been a popular frequency for long-range air-surveillance radar. There is also a near-by band, extending from 850 to 942 MHz, in which radar is authorized to operate. The U. S. Navy's ANEPS-49 uses this band. The initial motivation for pursuing the Senrad concept was to develop and demonstrate a radar that would be less vulnerable to electronic countermeasures than a conventional radar. For this reason, we chose to design Senrad to operate within the frequency range from 850 to 1400 MHz, a relative bandwidth of about 50% A radar, of course, is not normally allowed to operate without restrictions over such a wide bandwidth since there are other important military and civilian electromagnetic services that occupy this band. Senrad operated simultaneously within the 1215-1400 MHz band and the 850-942 MHz band to demonstrate capabilities not available with conventional narrow- band air-surveillance radars systems. ---------------------- Naval Research Laboratory Systems Aspects of Digital Beam Forming Ubiquitous Radar MERRILL SKOLNIK Systems Directorate June 28, http://www.dtic.mil/cgi-bin/GetTRDoc?AD=ADA403877&Location=U2&doc=GetTRDoc.pdf ----------------------------------- smotri gl. 2.13 M.Skolnik ,Radar izdanie 2008 goda http://www.scribd.com/doc/49249408/0071485473-Radar-Handbook3rd 2.13 Dynamic Range and A/D convesion cosiderations ----------------------------------- Dynamic Range and Stability requirement 4.24 ADC in Doppler radar http://www.scribd.com/doc/49249408/0071485473-Radar-Handbook3rd ...The most stressing dynamic range requirement is due to main beam clutter ,when searching for small low flying target ------------------------------------------- example 4.15 C/N 53 db na wisote RLS 1000 fut/300 metrow trebuetsja 12 bit dlja 63 db -------------------------------- 5.12 Glawa 5 Merrril Skolnik 2008 goda MULTIFUNCTIONAL RADAR SYSTEMS FOR FIGHTER AIRCRAFT 1.Real beam map 0.5 -10 mgz 2.Doppler beam sharp 5-25 mgz 3. SAR 10 -500 mgz 4.A-S range 1-50 mgz 5.PVU 1-10 mgz 6.TF/TA 3-15 mgz 7.Sea surface search 0.2 -500 mgz 8.Inverse SAR 5-100 mgz 9. GMTI 0.5-15 mgz 10.Fixed target track 1-50 mgz 11.GMTT 0.5 -15 mgz 12.Sea Surface track 0.2-10 mgz 13.Hi power Jam 1-100 mgz 14.CAl/A.G.C 1-500 mgz 15A-S data link 0.5-250 mgz -------------------------------------
milstar: МОСКВА, 17 апреля. /ТАСС/. Риски кооперации предприятий российского ОПК с иностранными поставщиками нужно снижать. Об этом заявил в пятницу президент России Владимир Путин на заседании Военно-промышленной комиссии. "Нужно снижать риски этой зависимости и риски этой кооперации. Вся цепочка производства стратегически важных материалов, компонентов, оборудования вплоть до доставки конечному потребителю должна быть локализована", - сказал глава государства. Путин дал высокую оценку работе ОПК России в 2014 и в первом квартале 2015 года "В отечественном ОПК местами сохраняется зависимость от внешних поставщиков. При осложнении международной обстановки эти участки могут давать сбои", - предупредил президент. Он отметил, что в 2014 году удалось выполнить практически все плановые задания Гособоронзаказа, и первый квартал 2015 года "закончился с положительным результатом". Путин указал, что сегодня крайне важно не просто замещать устаревшие производства, но и разработать перспективные импортозамещающие образцы военной техники. Глава государства добавил, что импортозамещение в ОПК - "серьезный вызов, на который должны ответить управленцы, инженеры, конструкторы, предприниматели и ученые". Путин уверен, что такая политика должна стать стимулом для новый научных разработок и технологических решений. Президент заметил, что это будет иметь эффект и для гражданского сектора.
milstar: Президент России провёл заседание Военно-промышленной комиссии. Обсуждался ход выполнения государственного оборонного заказа, а также вопросы импортозамещения в сфере оборонно-промышленного комплекса. В.Путин: Добрый день, уважаемые коллеги! Сегодня мы проводим очередное заседание Военно-промышленной комиссии. Обсудим наиболее важные вопросы для обороны и безопасности государства, наметим задачи развития оборонно-промышленного комплекса страны. Укрепление ОПК, повышение его эффективности – это один из базовых принципов и приоритетов государства, залог уверенного промышленного роста и основа для обеспечения обороноспособности. По результатам прошлого года практически все плановые задания закрыты. Сегодня утром мы обсудили итоги выполнения гособоронзаказа в первом квартале текущего года, проанализировали, что удалось сделать, какие проблемы и какие вопросы ещё остаются нерешёнными. В целом, по сути, первый квартал закончился с положительным результатом. Сегодня стоит задача не просто замещать устаревающую продукцию и модернизировать производство. Крайне важно разрабатывать перспективные импортозамещающие образцы военной техники. В отечественном ОПК, работающем на нужды нашей армии и флота, местами сохраняется зависимость от внешних поставщиков. При осложнении международной обстановки эти участки могут давать сбои – здесь никакие комментарии не нужны, и так всем всё понятно, – поэтому нужно снижать риски этой зависимости и риски этой кооперации. Подчеркну: вся цепочка разработки и производства стратегически важных материалов, компонентов и оборудования – вплоть до доставки конечному потребителю – должна быть локализована в России. И ещё на эту тему. Замещение импортных поставок в оборонной промышленности – это серьёзный вызов, на который должны ответить управленцы, инженеры, конструкторы, предприниматели и учёные. Вместе с тем такая политика должна стать стимулом для новых конструкторских разработок и технологических решений, для усиления кадрового потенциала оборонного комплекса и выхода на гражданские отрасли производства. Как вы знаете, в январе текущего года был подписан Указ о генеральном конструкторе по созданию вооружения, военной и специальной техники. Эти руководители получат дополнительные полномочия. За прошедшие три месяца были отобраны кандидаты для наделения этими полномочиями людей на должности генерального конструктора. Все без исключения – это очень достойные, зарекомендовавшие себя люди, имеющие большой опыт и результаты работы. Сегодня мы рассмотрим эти кандидатуры и примем по ним необходимые решения. И в заключение хотел бы напомнить, что в июне текущего года в России пройдёт Международный военно-технический форум «Армия-2015». Это ещё одна возможность и ещё одна площадка для диалога и контактов с нашими иностранными партнёрами, со специалистами, мы и в этой сфере ни от кого закрываться не собираемся. И, конечно, возможность для того, чтобы в сфере военно-технического сотрудничества с зарубежными странами сделать ещё дополнительный шаг вперёд. В рамках форума состоится, как вы знаете, масштабная выставка военной продукции, где возможности российского оружия и военной техники будут продемонстрированы, что называется, в деле. Давайте начнём работать. <…> 17 апреля 2015 года 16:15 Москва, Кремль
milstar: МОСКВА, 26 августа. /ТАСС/. Работа комиссии по импортозамещению не должна быть формальной. Об этом в ходе встречи с членами правительства заявил президент РФ Владимир Путин. "Нужно, чтобы работа этой комиссии не была формальной, она должна быть наполнена конкретным, реальным совершенно содержанием", - сказал Путин. http://oborona.gov.ru/news/view/6001
milstar: http://www.ti.com/product/ads54j60 16-Bit Resolution, Dual-Channel, 1-GSPS ADC Noise Floor: –159 dBFS/Hz Spectral Performance (fIN = 170 MHz at –1 dBFS): SNR: 70 dBFS NSD: –157 dBFS/Hz SFDR 86 db Related end equipment Radar and Antenna Arrays Broadband Wireless Cable CMTS, DOCSIS 3.1 Receivers Communications Test Equipment Microwave Receivers Software Defined Radio (SDR) Digitizers
milstar: Военное принципы цели ,концентрации и экономии сил Важнейшая задача в области процессоров -Создание отечественного специализированного процессора быстрой трансформации Фурье с высокой производительностью на единицу потребляемой мощности пример CSX700 Clearspeed применение РЛС с синтезированной апертурой ( SAR/ISAR) Головки самонаведения ракет ,АФАР ПАК ФА , спутники Кондор технология в России давно есть Необходима группа инженеров топологов Финансирование весьма небольшое- до 30 миллионов долларов
milstar: High-Performance GSPS Data Converters Improve RADAR & EW Architectures http://www.analog.com/en/education/education-library/webcasts/high-performance-gsps-data-converters.html
milstar: http://www.electronics.ru/files/article_pdf/0/article_323_74.pdf сегодня уже ряд изгото- вителей предлагают АЦП с производительностью свыше миллиарда выборок в секунду (GSPS) – вплоть до 3 и даже до 5 GSPS. Причем речь идет о серийной продукции с вполне доступными це- нами (сотни долларов). За счет чего достигается такое быстродействие?
milstar: AD9691 2*14 bit Low power consumption analog core, 14-bit, 1.25 GSPS dual ADC with 1.9 W per channel. 2. Wide full power bandwidth supports intermediate frequency (IF) sampling of signals up to 1.5 GHz --------------------------- http://www.analog.com/media/en/technical-documentation/data-sheets/AD9691.pdf SINAD 57.5 dBFS 985 mhz ENOB 9.6 bit SFDR -72 dBFS [url=http://www.analog.com/en/parametricsearch/10560#/p88=10000000|2600000000]http://www.analog.com/en/parametricsearch/10560#/p88=10000000|2600000000[/url]
milstar: AD9234 12 bit 500 msps/ 2*500 msps --------------------------- http://www.analog.com/media/en/technical-documentation/data-sheets/AD9234.pdf SINAD 63.1 dBFS 985 mhz ENOB 10.2 bit SFDR -75 dBFS
milstar: AD9680 1.25 gsps -500 msps 14 bit This device is designed for sampling wide bandwidth analog signals of up to 2 GHz. http://www.analog.com/media/en/technical-documentation/data-sheets/AD9680.pdf SINAD 63.6 dBFS 985 mhz ENOB 10.3 bit SFDR -75 dBFS 584$ 3.3 watt consum .power
milstar: AD9625 12 bit 2.6-2 GSPS 837 -624 $ 2 GSPS SINAD 59 dBFS 1000 mhz ENOB 9.3 bit SFDR -80 dBFS http://www.analog.com/media/en/technical-documentation/data-sheets/AD9625.pdf 2.6 GSPS 4 watt ,837 $
milstar: e2v EV12AS200ZPY 12 bit 1.5 GSPS SINAD 55.8 dBFS 1000 mhz 1.3 gsps ENOB 9 bit 1.3 gsps SFDR -68/57 dBFS http://www.e2v.com/resources/account/download-datasheet/1784
milstar: Description This system level design shows how two ADC12J4000 evaluation modules (EVMs) can be synchronized together using a Xilinx VC707 platform. The design document describes the required hardware modifications and device configurations, including the clocking scheme. Example configuration files are shown for each EVM. The FPGA firmware is described and the relevant Xilinx IP block configuration parameters are shown. Data taken on the actual hardware is shown and analyzed, showing synchronization within 50 ps without characterized cables or calibrated propagation delays. Features Demonstrates a typical phased array radar sub-system by showing synchronization of JESD204B giga-sample ADCs ----------------------------------------------------------------------------------------------------------- http://www.ti.com/tool/TIDA-00432
milstar: 24 NOVEMBER 2015 e2v develops its most advanced high performance, low noise Analog-to-Digital Converter (ADC) e2v has announced plans to launch a next generation 12-bit ADC that offers 5.4GSps, low latency and very low noise next year. e2v’s new EV12AS350 is set to be the only 12-bit resolution ADC on the market that combines signal digitization at 5.4GSps, input bandwidth in excess of 3GHz and latency as low as 26 clock cycles with a noise of -150dBm/Hz. Unlike other ADCs on the market, it will be free of non-harmonic spurs, creating a pure signal for coders to manipulate in a range of demanding applications. With the ability to use a simultaneous sampling mode to average 4 ADC cores and gain 6dB of Signal to Noise Ratio (SNR), the EV12AS350 will offer high resolution and high dynamic range in one component. These capabilities make it perfect for electronic warfare and test and measurement applications. Richard Gibbs, President of e2v Semiconductors, said, “We have utilized 20 years of e2v knowledge and design disciplines to develop what will be our most powerful ADC to date. Implementing this experience has allowed us to unveil an ADC with no non-harmonic spurs, which will allow coders to achieve previously unimagined performance in their systems.” Laurent Monge, VP and General Manager of e2v Semiconductors, said, “Very high demand from our customers for the demonstrator of this ADC encouraged us to develop the enhanced version of the EV12AS350 and commit to launching it as a full product that will be available for general sampling next year.” Visit www.e2v.com/EV12AS350 for preliminary documentation.
milstar: http://www.e2v.com/shared/content/resources/File/documents/broadband-data-converters/EV12AS350/EV12AS350ATP_PDS.pdf Single Channel ADC with 12-bit resolution using four interleaved cores enabling 5.4 Gsps conversion rate. Single 5.4 GHz Differential Symmetrical Input Clock 1000 mVpp Analog Input (Differential AC or DC Coupled) ADC Master Reset (LVDS) 2 conversion modes − 4 interleaved cores with staggered output data (equivalent to Mux 1:4) − Simultaneous sampling over 4 cores converting the same input signal with aligned outputs (can be used for averaging) LVDS Output format Digital Interface (SPI) with reset signal: − Standby Mode (full or partial) − Selection of data output swing − Test Modes − Chip configurations Power Supplies: single 4.8V, 3.3V and 1.8V Reduced clock induced transients on power supply pins due to BiCMOS Silicon technology Power Dissipation: 7 W EBGA380 Package 31x31mm (1.27 mm Pitch) Performance Analog input bandwidth (-3 dB): 2.4GHz Fsampling = 4.5 Gsps, (-3 dBFS) single tone − 4.5 Gsps, Fin = 1200 MHz, ENOB = 9.2 bit_FS over first Nyquist zone − 4.5 Gsps, Fin = 1200 MHz, SNR = 57.8 dBFS over first Nyquist zone − 4.5 Gsps, Fin = 1200 MHz, SFDR = 69 dBFS over first Nyquist zone − 4.5 Gsps, Fin = 2240 MHz, ENOB = 8.6 bit_FS over first Nyquist zone − 4.5 Gsps, Fin = 2240 MHz, SNR = 54.6 dBFS over first Nyquist zone − 4.5 Gsps, Fin = 2240 MHz, SFDR = 63 dBFS over first Nyquist zone Fsampling = 5.4 Gsps, (-3 dBFS) single tone − 5.4 Gsps, Fin = 1200 MHz, ENOB = 8.9 bit_FS over first Nyquist zone − 5.4 Gsps, Fin = 1200 MHz, SNR = 57.6 dBFS over first Nyquist zone − 5.4 Gsps, Fin = 1200 MHz, SFDR = 63 dBFS over first Nyquist zone Latency: 26 clock cycles Applications High Speed Data Acquisition Direct RF Down conversion Ultra Wideband Satellite Digital Receiver 16 Gbps pt-pt microwave receivers High energy Physics Automatic Test Equipment High Speed Test Instrumentation LiDAR (Light Detection And Ranging) Software Design Radio 1 EV12AS350A DATASHEET – PRELIMINARY
milstar: http://www.ti.com/lit/ds/symlink/adc12j2700.pdf ADC12Jxx00 12-Bit 1.6 or 2.7 GSPS ADCs With Integrated DDC SFDR 2700 mhz 66.7 dBFS Fin =1500 mhz , -1 dBFS ENOB -8.4 bit,Snad -52.4 db Power cons -1.8 watt VQFN 68 10 mm *10 mm The ADC12J1600 and ADC12J2700 devices are based on an ultra high-speed ADC core. The core uses an interleaved calibrated folding and interpolating architecture --------------------------------------------------------------- that results in very high sampling rate, very good dynamic performance, and relatively low-power consumption 950$ http://www.ti.com/lsds/ti/data-converters/analog-to-digital-converter-products.page#p84=12;12&p1089=1000000000;5000000000
milstar: When 1 + 1 = +3 (dB): Averaging ADC Channels to Improve NSD http://electronicdesign.com/analog/when-1-1-3-db-averaging-adc-channels-improve-nsd Averaging techniques can improve system performance through careful ADC configuration and back-end data processing. Although this can be achieved with discrete converter solutions, there are reasons why a more robust approach involves multichannel ADCs. In order to fully understand the approach, the benefits and associated tradeoffs must be Ian Beavers, Applications Engineer, Analog Devices Inc. weighed accordingly. These will be described along with the mathematical processing that makes it a reality. ------------------ Increasing SNR by 6 dB would require four averaged ADCs. --------------- Using two ADC channels within the same device provides the best path for success with this method, since the input full scale, gain, offset, and bandwidth are typically well-matched within a single piece of silicon. Using two separate discrete ADCs will make the exercise more challenging, because there’s greater potential for slight input and device mismatch, which will degrade the full +3-dB benefit.
milstar: Theoretically, the SNR can be increased by 3 dB (one-half-bit) with two different methods. One option is to double the sampling rate and digitally filter the output (e.g., with an FIR decimation filter). The second option is to parallel two ADCs and simply average the digital output. At times, doubling the sampling rate is the less desirable option because faster ADCs may not yet be available. http://www.eetimes.com/document.asp?doc_id=1272377 The concept of averaging the output of separate ADCs for SNR improvement was verified using three ADCs tied to an FPGA, which then outputs the conversion results of each individual ADC or two or three ADCs averaged together, Figure 1. By using three ADCs instead of one, the SNR ideally improves by 4.8 dB, as derived below, which boosts the 14-bit ADC (SNR ∼74dB) to a 16-bit ADC level (SNR ∼79dB). The analog input signal was split and fed into three ADCs which were sampled with a common clock source. An FPGA performed the averaging function as well as a level translation of the digital output from DDR-LVDS to LVTTL (double-data-rate, low-voltage differential signal to low-voltage TTL). The averaging technique reduces uncorrelated white noise, but has no effect on distortions inherent to the ADC design that might be common to all three ADCs. If, for example, the ADC creates a large third-order distortion product, it will show up in each ADC used and averaging won't reduce it. Therefore, averaging only improves SNR, but not spurious free dynamic range (SFDR). This article shows how averaging the outputs of multiple high-speed ADCs can be used to improve data converter SNR. While an alternate technique of oversampling the input signal using faster ADCs is possible, the averaging approach seems preferable because faster ADCs which enable oversampling may not be available, and lower-speed ADCs used in an averaging approach may have better initial SNR specifications and lower power. This article examined the averaging approach. In summary, averaging the outputs of multiple ADCs can be used to improve state-of-the-art data converters. ADCs with low internal aperture jitter help maximize the SNR gain. With proper care taken with the input matching circuit and clock jitter, the SNR gains can match the 4.8 dB improvement predicted by theory when averaging three ADCs.
milstar: http://www.e2v.com/shared/content/resources/File/documents/broadband-data-converters/EV12AS350/EV12AS350ATP_PDS.pdf DYNAMIC PERFORMANCE over first Nyquist zone (single tone at -6 dBFS) 4 cores in parallel (Simultaneous mode) 1st value is without averaging / 2nd value is with averaging of 4 cores 4.5 Gsps external clock, each core running at 1.125 Gsps Fin 1200 mhz ENOB 9.5/10.1 SFDR 79/79 dBFS SINAD 59/62 dBFS Aperture delay 60 pikosec
milstar: 4 GSPS The ADC12J4000 device is based on an ultra high-speed ADC core. The core uses an interleaved calibrated folding and interpolating architecture ------------------------------------------------------------------------------------- that results in very high sampling rate, very good dynamic performance, and relatively low-power consumption. ADC12J4000 12-Bit 4GSPS ADC With Integrated DDC Decimation Factors from 4 to 32 (Complex Baseband Out) • Usable Output Bandwidth of 800 MHz at 4x Decimation and 4000 MSPS • Usable Output Bandwidth of 100 MHz at 32x Decimation and 4000 MSPS – Noise Floor: −149 dBFS/Hz or −150.8 dBm/Hz http://www.ti.com/lit/ds/symlink/adc12j4000.pdf EXAMPLE VALUES Signal center frequency - 2500 MHz Signal bandwidth - 100 MHz Signal nominal amplitude –7 dBm Signal maximum amplitude 6 dBm Minimum SINAD (in bandwidth of interest) 48 dBc Minimum SFDR (in bandwidth of interest) 60 dBc
milstar: September 2014 GSPS Data Converters to the Rescue for Electronics Surveillance and Warfare Systems! By Analog Devices http://www.mpdigest.com/issue/Articles/2014/Sept/Analog/default.asp
milstar: Figure 5. The output spectrum of the AD9625, clocked at 2.5 GSPS and with an input tone close to 1 GHz. (a) Sequential three-way interleaving; SNR = 60 dBFS, the SFDR = 72 dBc is limited by the third harmonic, near 500 MHz; however, a number of interleaving spurs are visible all across the spectrum. (b) Three-way interleaving with random channel shuffling; SNR = 58 dBFS, while the SFDR = 72 dBc is still set by the third harmonic, all the interleaving spurs have been eliminated by spreading their power over the noise floor. http://www.analog.com/library/analogDialogue/archives/49-07/interleaving_adcs.html The AD9625 is a 12-bit/2.5 GSPS three-way interleaved ADC. The mismatches between the three channels are calibrated in order to minimize the interleaving spurs. An example of its output spectrum with an input close to 1 GHz is depicted in Figure 5(a). In this spectrum, besides the ~1 GHz input tone, it is possible to see the channels’ 2nd and 3rd harmonic distortion near 500 MHz and the 4th harmonic distortion near the fundamental. The interleaving mismatch calibration substantially minimizes the power of the interleaving spurs and a large set of additional residual small spurious tones is visible across the entire spectrum. In order to further reduce such residual spurious content, channel randomization is introduced. A fourth calibrated channel is added and the four channels are then three-way interleaved in randomly changing order by intermittently swapping one of the interleaved channels with the fourth one. One can liken that to a juggler playing with three Skittles up in the air while a fourth one is swapped in every so often. By doing so, the residual interleaving spurious power is randomized and spread out over the noise floor. As shown in Figure 5(b), after channel randomization, the interleaving spurs have nearly disappeared, while the power of the noise has marginally increased, hence degrading the SNR by 2 dB. Note, of course, that while the second spectrum shown in Figure 5(b) is considerably cleaner of distortion tones, the shuffling cannot affect the 2nd, 3rd, and 4th harmonic since these aren’t interleaving spurs.
milstar: Handling 30 differential LVDS pairs per ADC can be challenging to route and maintain matched lengths on a system layout. The equivalent data can be sent with only six or eight differential lanes using JESD204B, a high speed serialize/deserialize (SERDES) standard designed specifically for converter interfaces. JESD204B provides a means to output data at high speeds on fewer data lines without the matched timing board complexities of many high speed LVDS lanes. Since the data sent over JESD204B is framed based on an embedded clock and control characters, the routing of the lower count serial lanes is much more forgiving of timing skew than LVDS, as seen in Figure 2. This removes the need to spend countless hours working to tweak output timing on every I/O of the system PCB. In addition, JESD204B offers informational “control bits” of auxiliary data that can be appended to each analog sample to help characterize the downstream processing. In this fashion, trigger time stamping and overrange conditions can be tagged per sample so that a back-end FPGA can have further intelligence about data alignment and its validity. http://www.analog.com/media/en/technical-documentation/technical-articles/Gigasample-ADCs-Run-Fast-to-Solve-New-Challenges-MS-2702.pdf
milstar: The AD-FMCOMMS6-EBZ platform is a 400MHz to 4.4GHz receiver (1350MHz to 1650MHz with installed filters) in a VITA57-compliant form factor. The receiver integrates the AD9652 dual 16-bit A/D converter, ADL5566 RF/IF dual differential amplifier and ADL5380 quadrature demodulator. A complete design support package is available for the AD-FMCOMMS6-EBZ, and includes schematics, layout files, noise analysis worksheet, FPGA HDL (hardware description language) code, and software drivers. The AD-FMCOMMS6-EBZ incorporates an I/Q demodulator to implement a direct conversion or zero IF architecture in which just one frequency translation is required, compared to a super-heterodyne receiver that must perform several frequency translations. According to ADI, a single frequency translation is advantageous because it "reduces receiver complexity and the number of conversion stages needed, which in turn increases performance and reduces power consumption". The design also avoids image rejection issues and unwanted mixing by adding an amplification stage to maintain the full-scale input to the A/D converter. The image rejection inherent to the I/Q modulation scheme removes the need for an expensive anti-aliasing filter. The on-board local oscillator and converter clock share the same reference signal to prevent smearing. The AD-FMCOMMS6-EBZ receiver development platform incorporates a full direct-receive signal chain path and has a bandwidth of 220MHz with a pass-band flatness of +/- 1.0 dB. The RF input range of the ADL5380 demodulator is 400MHz to 6GHz and is powered by a single 5V supply. The ADL5566 4.5GHz dual differential amplifier is optimized for IF and dc applications and provides a gain of 16dB. The AD9652 dual 16-bit, 310MSPS A/D converter achieves the industry’s lowest noise at the highest speed; this level of performance enables target identification at a much longer range. The SNR and SFDR measured at an IF of 145MHz are 64dB and 78dBc, respectively. http://www.electronicsweekly.com/news/products/rf-microwave-optoelectronics/direct-conversion-receiver-means-smaller-radars-says-adi-2014-12/
milstar: The AD9680 completes the chain and is one of the latest high speed converters. Based on 65 nm CMOS, the device supports sampling at up to 1 GSPS at a resolution of 14 bits. Using higher sample rates and the bandwidths of gigasample converters, the AD9680 potentially supports undersampling an IF in excess of 1 GHz. This supports the continued trend of moving the digital conversion point of the system closer to the antenna and increasing the flexibility of the system. The device not only provides industry-leading SFDR and SNR but also incorporates digital downconversion (DDC) signal processing, to provide customizable output bandwidths. The digital signal processing configurability of the AD9680 ADC enables the device to support wideband surveillance, as well as narrow-band functionality. With the incorporated DDC disabled and bypassed, it can support an instantaneous surveillance bandwidth in excess of 500 MHz. --------------------------------------------------- Utilizing the DDCs, the digital numerically controlled oscillator (NCO) can be set to digitally mix a narrow-band IF to baseband before configurable decimation filters reduce the data rate, supporting output data bandwidths down to 60 MHz when the device is operated at the maximum ADC sample rate -------------------------------------------------------------------- . Thedigital signal processing improves the SNR of the system for the lower bandwidth, again supporting the flexibility needed for a configurable wideband and narrow-band signal chain. http://www.analog.com/library/analogDialogue/archives/49-06/Multifunction_Dilemma.pdf
milstar: AD9680 1.2 GSPS 2*14 bit Noise density = −154 dBFS/Hz at 1 GSPS SFDR = 85 dBFS at 340 MHz, 80 dBFS at 1 GHz SNR = 65.3 dBFS at 340 MHz (AIN = −1.0 dBFS), 60.5 dBFS at 1 GHz (AIN = -1.0 dBFS) http://www.analog.com/en/products/analog-to-digital-converters/high-speed-ad-10msps/high-if-ad-converters/ad9680.html#product-overview
milstar: RF Sampling 4-GSPS ADC With 8-GHz DC-Coupled, Fully-Differential Amplifier Reference Design http://www.ti.com/lit/ug/tiduaz9/tiduaz9.pdf SFDR 1747 mhz -61 dBFS SINAD 1747 mhz -50.37 dBFS ------------------------- SFDR 197.77 mhz -67.34 dBFS SINAD 197.77 mhz -53.65 dBFS
milstar: ADC12D1800RF 12-Bit, Single 3.6 GSPS RF Sampling ADC Resolution: 12 Bits 1800 MSPS Dual ADC – Interleaved 3.6 GSPS ADC (all typical) • New DESCLKIQ Mode for High Bandwidth, High • IMD3 (Fin = 2.7GHz at -13dBFS) –62 dBc • Noise Floor Density -155.0 dBm/Hz • • Power 4.29 W – Dual 1800 MSPS ADC, Fin = 498 MHz Inputs • ENOB 9.3 Bits (typ) • SNR 58.1 dB (typ) Adjust • SFDR 71.7 dBc (typ) • Test Patterns at Output for System Debug • Power per Channel 2.15 W (typ) 292 BGA 27*27 mm http://www.ti.com/lit/ds/symlink/adc12d1800rf.pdf
milstar: http://www.e2v.com/shared/content/resources/File/documents/broadband-data-converters/EV12AS350/EV12AS350ATP_PDS.pdf 4 core parallel ,2 value with averaging 4 core Fin 1200 mHZ -1 dBFS over first Nyquist zone ENOB 9/9.5 bit SFDR - 67/67 dBFS SNR - 56.6/60.1 dBFS SINAD -56/59 dBFS
milstar: The Nyquist bandwidth is defined to be the frequency spectrum from DC to fs/2. The frequency spectrum is divided into an infinite number of Nyquist zones, each having a width equal to 0.5fs as shown. In practice, the ideal sampler is replaced by an ADC followed by an FFT processor. The FFT processor only provides an output from DC to fs/2, i.e., the signals or aliases which appear in the first Nyquist zone. http://www.analog.com/media/cn/training-seminars/design-handbooks/36701482523116527500547882375sect4.pdf
milstar: Sampling signals above the first Nyquist( 0.5 Fs- Fs ) zone has become popular in communications because the process is equivalent to analog demodulation. It is becoming common practice to sample IF signals directly and then use digital techniques to process the signal, thereby eliminating the need for the IF demodulator. Clearly, however, as the IF frequencies become higher, the dynamic performance requirements on the ADC become more critical. ---------------------------------------------------------------------- The ADC input bandwidth and distortion performance must be adequate at the IF frequency, rather than only baseband. This presents a problem for most ADCs designed to process signals in the first Nyquist zone, therefore an ADC suitable for undersampling applications must maintain dynamic performance into the higher order Nyquist zones. http://www.analog.com/media/cn/training-seminars/design-handbooks/36701482523116527500547882375sect4.pdf
milstar: Why would we use a DDC over Analogue Techniques? Plainly a DDC is implementing something which could be done in analogue – it’s sometimes good to stop and check why we’d want to do this. The DDC is typically used to convert an RF signal down to baseband. It does this by digitising at a high sample rate, and then using purely digital techniques to perform the data reduction. Being digital gives many advantages, including: • Digital stability – not affected by temperature or manufacturing processes. With a DDC, if the system operates at all, it works perfectly – there’s never any tuning or component tolerance to worry about. • Controllability – all aspects of the DDC are controlled from software. The local oscillator can change frequency very rapidly indeed – in many cases a frequency change can take place on the next sample. Additionally, that frequency hop can be large – there is no settling time for the oscillator. • Size. A single ADC can feed many DDCs, a boon for multi-carrier applications. A single DDC can be implemented in part of an FPGA device, so multiple channels can be implemented – or additional circuitry could also be added. However, there are some disadvantages: • ADC speeds are limited. It is not possible today to digitise high-frequency carriers directly. There are techniques to extend the range of ADCs, but often it is simpler to use analogue circuits to bring the carrier down to an IF that digital circuits can then manage. =============================================== к первой или второй промежуточной частоте • ADC dynamic range is limited. In many communications systems, the signal’s amplitude can vary greatly. Fast ADCs often only have 12bits of resolution – giving an absolute maximum dynamic range of 72dB. It is often better to use analogue circuits in conjunction with the ADC to implement AGC functions to ensure that this range is best used. In time, more and more systems will use predominantly digital technology. However, the high speeds of many communication systems will ensure that a hybrid approach, using analogue and digital, will be the best route for many systems for a long time to come. The quest for more spectral space will ensure that new systems will use ever higher frequencies, ensuring that analog approaches will be around for a long time to come! http://www.hunteng.co.uk/pdfs/tech/ddctheory.pdf
milstar: Разрешающая способность БРЛС Н035 "Ирбис-Э" - 1 метр это полоса сигнала 250 Mhz ----------------------------------- AD9680 2*14 bit ,1.25 GSPS http://www.analog.com/media/en/technical-documentation/data-sheets/AD9680.pdf JESD204B (Subclass 1) coded serial digital outputs 1.65 W total power per channel at 1 GSPS (default settings) SFDR at 1 GSPS = 85 dBFS at 340 MHz, 80 dBFS at 1 GHz SNR at 1 GSPS = 65.3 dBFS at 340 MHz (AIN = −1.0 dBFS), 60.5 dBFS at 1 GHz (AIN = −1.0 dBFS)
milstar: SNR is always added in RMS fashion, like power: If the ADC and amplifier plus filter SNRs are equal; the overall SNR is 3 dB less than the ADC. With higher SNR performance from the amplifier and filter, the SNR asymptotically approaches that of the data converter. A 0.1 dB degradation is achieved when the amplifier and filter are optimized for 15 dB better SNR than the ADC. http://www.electronicproducts.com/Analog_Mixed_Signal_ICs/Standard_Linear/Analyzing_ADC_SNR_SFDR_in_high-speed_apps.aspx As previously mentioned, all high-performance ADCs use differential inputs. The key reasons are: 1. Better noise rejection. 2. Double the signal amplitude versus single-ended inputs of the same amplitude. 3. Even-order distortion suppression. Rejecting system noise and effectively doubling the input signal amplitude provide the best SNR performance, while suppression of even-order distortion provides higher SFDR performance. Architectures for driving differential input ADCs Signals in systems are often single ended and must be converted to differential for driving the ADC. There are three ways to do this: 1. Transformers or baluns are excellent at converting single-ended inputs to differential. They require no power, add no noise, and are very linear. The turns ratio can be used to step the voltage up or down. They do not pass dc, but many provide a secondary center tap where the ADC input common-mode-bias can be applied. Their primary drawback is flatness versus frequency. Many times an amplifier is still required and radio frequency (RF)-type amplifiers are often used, especially at higher frequencies, but may require high power to achieve low even-order harmonics. 2. Single-ended op amps can be used in various configurations. One suitable for lower frequencies uses a non-inverting op amp to provide the in-phase output, while also driving an inverting op amp to provide the out-of-phase output. The challenge with this architecture is the two outputs are inherently mismatched and balance cannot be maintained as frequency increases.
milstar: Surveillance and Tracking Radar systems require dynamic range of about 80 dB for the signal. This fact implies that, for this application, with an operating RF frequency of 5 GHz and 14 bit ENOB, the clock jitter should be as low as 0.8 fs and pulse length less than 0.47 ps [4] that is actually very challenging. In this case the digital beam forming concept can be adopted. An array of M digital receivers (up to 100 in new systems) is employed; due to the recombination gain (=10 log10(M)), the requirement on dynamic range is relaxed to 60 dB. http://www.ircphonet.it/research/publication/private_pdf/papers_447.pdf
milstar: The Lynx SAR operates in the Ku-Band anywhere within the range 15.2 GHz to 18.2 GHz, with 320 W of transmitter power. It is designed to operate and maintain performance specifications in adverse weather, using a Sandia derived weather model that includes 4 mm/hr rainfall. It forms fineresolution images in real-time and outputs both NTSC video as well as digital images. The front-end microwave components include a TWTA capable of outputting 320 W at 35% duty factor averaged over the Lynx frequency band, and an LNA that allows an overall system noise figure of about 4.5 dB. http://www.sandia.gov/RADAR/files/spie_lynx.pdf Image formation in all SAR modes is accomplished by stretch processing[2], that is, de-ramping the received chirp prior to digitizing the signal. After the ADCs, presumming is employed to maximize SNR in the image and minimize the load on the subsequent processors. The algorithm used thereafter is an expanded version of the Sandia developed OverlappedSubaperture (OSA) processing algorithm[1], followed by Sandia developed Phase-Gradient Autofocus (PGA)[3]. Either complex images or detected images can be exported to View Manager software.
milstar: Why would we use a DDC over Analogue Techniques? Plainly a DDC is implementing something which could be done in analogue – it’s sometimes good to stop and check why we’d want to do this. The DDC is typically used to convert an RF signal down to baseband. It does this by digitising at a high sample rate, and then using purely digital techniques to perform the data reduction. Being digital gives many advantages, including: Digital stability – not affected by temperature or manufacturing processes. With a DDC, if the system operates at all, it works perfectly – there’s never any tuning or component tolerance to worry about. Controllability – all aspects of the DDC are controlled from software. The local oscillator can change frequency very rapidly indeed – in many cases a frequency change can take place on the next sample. Additionally, that frequency hop can be large – there is no settling time for the oscillator. Size. A single ADC can feed many DDCs, a boon for multi-carrier applications. A single DDC can be implemented in part of an FPGA device, so multiple channels can be implemented – or additional circuitry could also be added. However, there are some disadvantages: ADC speeds are limited. It is not possible today to digitise high-frequency carriers directly. There are techniques to extend the range of ADCs, but often it is simpler to use analogue circuits to bring the carrier down to an IF that digital circuits can then manage. ADC dynamic range is limited. In many communications systems, the signal’s amplitude can vary greatly. Fast ADCs often only have 12bits of resolution – giving an absolute maximum dynamic range of 72dB. It is often better to use analogue circuits in conjunction with the ADC to implement AGC functions to ensure that this range is best used. In time, more and more systems will use predominantly digital technology. However, the high speeds of many communication systems will ensure that a hybrid approach, using analogue and digital, will be the best route for many systems for a long time to come. The quest for more spectral space will ensure that new systems will use ever higher frequencies, ensuring that analog approaches will be around for a long time to come! http://www.hunteng.co.uk/support/ddctheory.htm
milstar: The LTC2217 is a 105Msps sampling 16-bit A/D converter designed for digitizing high frequency, wide dynamic range signals with input frequencies up to 400MHz. The input range of the ADC is fixed at 2.75VP-P. The LTC2217 is perfect for demanding communications applications, with AC performance that includes 81.3dBFS Noise Floor and 100dB spurious free dynamic range (SFDR). Ultra low jitter of 85fsRMS allows undersampling of high input frequencies while maintaining excellent noise performance http://www.linear.com/product/LTC2217 The LTC®2107 is a 16-bit, 210Msps high performance ADC. The combination of high sample rate, low noise and high linearity enable a new generation of digital radio designs. The direct sampling front-end is designed specifically for the most demanding receiver applications such as software defined radio and multi-channel GSM base stations. The AC performance includes, SNR = 80dBFS, SFDR = 98dBFS. Aperture jitter = 45fsRMS allows direct sampling of IF frequencies up to 500MHz with excellent performance. http://www.linear.com/product/LTC2107
milstar: The large bandwidths typical of high-IF sampling A/Ds also allow traditional analog hardware functions to be performed in the digital domain. In many communication systems, the incoming signal is split into I and Q channels which forces the use of two A/D converters. With high bandwidth and high IF converters, the signal can remain within a single channel through the converter and then be split and phase-shifted by subsequent digital circuitry, such as a digital down conversion (DDC) IC. By performing the quadrature demodulation in the digital domain, the split receive path is not needed, thus removing a converter, mixer and the requisite filtering from the architecture. Another benefit of sampling at higher frequencies is that in systems where large bandwidths are not required, the high-IF sampling of the faster converters can be used to gain SNR performance using of decimation. When decimating an A/D converter's output, you essentially throw away a periodic number of samples. Every time the output is decimated by a factor of two, where half the samples are removed, the SNR is improved by three dB. The cost is that the effective sample rate is now halved and, therefore, so is the available bandwidth. For example, suppose a system requires only 20 MHz of bandwidth, but the form factor needs to be small. It is possible with today's fastest 14-bit A/D converter to sample this 20 MHz of bandwidth at 200 MSPS with the center input frequency being 350 MHz, a reasonable output for an RF-to-IF mixing stage. Choosing this frequency for the IF centers the signal band in the converter's Nyquist zone, which spans 300 to 400 MHz. With the signal bandwidth residing in the 340-360 MHz range, the AAF has 40 MHz on either side of the signal to operate. From the contour plots in Figure 1, a converter can achieve 69 dBFS SNR and 73 dBc SFDR at this sample rate and input frequency. http://www.eetimes.com/document.asp?doc_id=1272390 With only 20 MHz of bandwidth to sample, a DDC's numerically controlled oscillator (NCO) could mix the signal to the I and Q bands. In turn, this allows the 200 MSPS sample rate to be decimated by a factor of four to an effective sample rate of 50 MSPS, increasing the SNR by 6 dB to 75 dBFS. Increased signal-chain requirements for high-IF sampling While implementing high-IF sampling solutions can lower component count and save board space, increasing the A/D input frequency does place more stringent demands on the analog signal chain than does low-IF sampling. In the above example, note that placing the center IF at 350 MHz centers the bandwidth in a Nyquist zone and provides 40 MHz of room for the AAF. Although filtering a 20-MHz band centered in a 100-MHz Nyquist zone is generally easier than doing so in one which is 50-MHz wide, doing so at 350 MHz presents a challenge. Op amps tend to degrade in performance at such IF frequencies, http://www.eetimes.com/document.asp?doc_id=1272390
milstar: GSPS ADCs that provide a high wideband SFDR, without the interleaving artifacts that have limited system performance in the past, are now available. The AD9680 is a dual-channel, 14-bit, 1 GSPS ADC that achieves SFDR of 78 dBc with a 1 GHz input. The AD9625 is a 12-bit, 2-GSPS ADC that offers typical wideband SFDR of 80 dBc with a 1 GHz input. SFDR is an important and key performance metric in GSPS and ADCs. Wideband SFDR is typically limited by the second or third harmonic of the fundamental signal. Single monolithic pipeline ADCs and other advanced architectures are advancing a new frontier in high performance GSPS converters. They do not exhibit the interleaving spurs in the frequency domain that have historically been present within ADC architectures in the GSPS space. http://www.analog.com/media/en/technical-documentation/technical-articles/Understanding-Spurious-Free-Dynamic-Range-in-Wideband-GSPS-ADCs-MS-2660.pdf
milstar: LTC2107 PGA= 0 p-p 2.5 v,PGA =1 p-p 1.6v 141 mhz -1 dBFS SINAD 78.7 db, 76.7 db SFDR 2hd harm. 87.5db 95.5 db http://cds.linear.com/docs/en/datasheet/2107fb.pdf
milstar: AV107 Phased-Array Radar-Receiver EW-ESM AV107 Phased-Array Radar-ReceiverEW-ESM AV121 Phased-Array Radar Receiver EW-ESM MIMO http://www.apissys.com/products
milstar: LTC2387 18 bit 15 msps http://cds.linear.com/docs/en/datasheet/238718fa.pdf 1mhz SINAD -94.5db SFDR -102 db
milstar: How to Oversample 5 MSPS, 18-Bit/16-Bit Precision SAR Converters to Increase Dynamic Range by Maithil Pachchigar http://www.analog.com/media/en/technical-documentation/application-notes/AN-1279.pdf The AD7960 and AD7961 data sheets list a typical dynamic range of 100 dB and 96 dB, respectively, using a 5 V reference. Therefore, in theory, oversampling by 256× increases the dynamic range by 24 dB. In reality, the measured oversampled dynamic range of these devices is 123 dB and 120 dB, respectively (see Figure 5 and Figure 7), with no input signal when oversampled by 256× at an output data rate of 19.53 kSPS
milstar: http://www.intersil.com/content/dam/Intersil/documents/isla/isla216s.pdf intersil isla216 16-Bit, 250/200/130 MSPS JESD204B High Speed Serial Output ADC 250 msps ain -2dbfs --------------------------- Fin 190 mhz ENOB 11.95 bit SINAD-73.9 db SFDR -82 db -------------------- http://www.analog.com/media/en/technical-documentation/data-sheets/AD9467.pdf ad9467-200/250 msps fin 170 mhz Ain -1dbfs SINAD-74.1/75.6 db SFDR -95/90 db ENOB 12/12.3bit -------------- LTC2107 http://cds.linear.com/docs/en/datasheet/2107fb.pdf Ain -1dbfs 141 mhz SINAD -78.7/76.7 db SFDR -87.5/95.5 db
milstar: Comparison of GS/s Analog-to-digital Converters Enhanced by ADX4 http://spdevices.com/index.php/adx4-comparison
milstar: http://spdevices.com/index.php/linearization Linearization of ADCs - ADL
milstar: ENOB 13 bit by BW 10 mhz e2v 12bit as200 http://www.embedded.com/print/4370321 System performance The performance of the system can be enhanced even further using post processing and real-time techniques, such as integral nonlinearity (INL) correction and using dither to improve SFDR. The shape of the INL curve plays a large part in the harmonic performance of the ADC. By characterizing this INL and using a look-up table (LUT) in the interface FPGA, the INL can be minimized, which brings benefits for the SFDR performance. The look-up table correction is a simple subtraction or addition of the measured INL value for the code. Using this technique has very little impact on the size of the FPGA and no impact on throughput. In some cases, the addition of a LUT for INL correction can improve SFDR by 10dB. The SFDR can also be improved by adding an out-of-band noise source to the input data. This can simply be a low-pass-filtered noise generator added to the input signal using a multi-port transformer. This has the effect of moving the input signal around the input scale of the ADC, which reduces the INL effect and improves SFDR (see Figure 4).
milstar: http://cds.linear.com/docs/en/datasheet/238718fa.pdf 15Msps Throughput Rate n No Pipeline Delay, No Cycle Latency n 95.7dB SNR (Typ) at fIN = 1MHz n 102dB SFDR (Typ) at fIN = 1MHz n Nyquist Sampling Up to 7.5MHz Input
milstar: http://www.analog.com/media/en/technical-documentation/data-sheets/AD9625.pdf str.33 The AD9625 architecture includes two DDCs, each designed to extract a portion of the full digital spectrum captured by the ADC. Each tuner consists of an independent frequency synthesizer and quadrature mixer; a chain of low-pass filters for rate conversion follows these components. Assuming a sampling frequency of 2.500 GSPS, the frequency synthesizer (10-bit NCO) allows for 1024 discrete tuning frequencies, ranging from −1.2499 GHz to +1.2500 GHz, in steps of 2500/1024 = 2.44 MHz. The low-pass filters allow for two modes of decimation. • A high bandwidth mode, 240 MHz wide (from −120 MHz to +120 MHz), sampled at 2.5 GHz/8 = 312.5 MHz for the I and Q branches separately. The 16-bit samples from the I and Q branches are transmitted through a dedicated JESD204B interface. • A low bandwidth mode, 120 MHz wide (from −60 MHz to +60 MHz), sampled at 2.5 GHz/16 = 156.25 MHz for the I and Q branches separately. The 16-bit samples from the I and Q branches are transmitted through a dedicated JESD204B interface. By design, all of the blocks operate at a single clock frequency of 2.5 GHz/8 = 312.5 MHz. Each filter stage includes a gain control block that is programmable by the user. The gain varies from 0 dB to 18 dB, in steps of 6 dB .... Filter performance is shown in Figure 83 and Figure 84. The filter yields an effective bandwidth of 120 MHz, with a transition band of 156.5 MHz − 120 MHz = 36.5 MHz. Therefore, the two-sided complex bandwidth of the filter is 240 MHz. A rejection ratio of 85 dB ensures that the seven aliases that fold back into the pass band yield an SNR of 85 dB − 10log10(7) = 76.5 dB, which ensures that the aliases remain sufficiently below the noise floor of the input signal. The pass-band ripple is ±0.05 dB, as shown in Figure 84.
milstar: Three e2v space grade data converter families have been awarded QMLV certification from the U.S. Defense Logistics Agency (DLA). The QMLV space certification will make it even easier for global space programs to adopt e2v’s world leading data converters. The certification, awarded to one Analog-to-Digital (ADC) and two Digital-to-Analog (DAC) families, reduces the amount of time and investment required by customers to test these e2v products. Richard Gibbs, president of e2v Semiconductors, said, “QMLV product listing is becoming more and more important to our customers as it significantly reduces their testing time. The certification of these products shows our commitment to the space industry and contributes towards the building of a comprehensive QML semiconductor portfolio.” With over 3,000 e2v data converter flight models currently in space, the ability to reduce customer testing time by almost 50 percent will further expand e2v’s semiconductor space presence. The newly certified products are all true single core devices, providing outstanding linearity and microwave capability for software defined RF systems in space. Suitable applications for these data converters include satellite communications, SAR imaging, GNSS navigation satellites and other forms of scientific space-borne instruments. The QMLV listing of these parts, in addition to the QMLV ratings of e2v’s manufacturing facilities in France and the United States, reinforces e2v’s commitment to the space market. e2v played a significant role in defining the recently released QMLY certification, working closely with NASA, and these particular ADCs and DACs already appear on the European Space Agency’s preferred parts list. November 9, 2015 http://www.microwavejournal.com/articles/25447-e2v-space-grade-data-converters-receive-qmlv-certification
milstar: A single-core architecture also has advantages in terms of latency. Fore examples, latencies as low as 3 clock cycles as found with the EV12AS200 [2] are very useful in applications such as EW and tracking systems. http://www.embedded.com/print/4370321 wo key specifications that are important for ADCs that serve in L-band applications are spectral purity and noise floor. Spectral Purity A true single-core architecture has significant advantages because it does not rely on internal interleaving to achieve a 1.5GS/s update rate. Hence, no form of calibration is required before or during operation over an extended temperature range. (One feature of interleaved ADCs is their prominent interleaving spurs. The offset mismatch will produce a spur of a fixed frequency; however, gain and phase mismatches will produce spurious frequencies that depend on the input signal frequency. Indeed, calibration is sometimes requested in ADCs using internal interleaving to avoid spurious free dynamic range performance degradation due to misalignment of gain, offset, and sampling aperture delays. ) The single-core advantage can be seen in the spectral purity plot shown in Figure 2. The choice of the frequency is made so that the main signal and its harmonics are close together in the FFT plot. This leaves the rest of the spectrum free to display any other non-signal related spurious signals for example clock spurs. An interleaved ADC may well display spurs in this region but we can see that he signal core shows a spur free zone and a spectral purity of 90dBc. A single-core architecture also has advantages in terms of latency. Fore examples, latencies as low as 3 clock cycles as found with the EV12AS200 [2] are very useful in applications such as EW and tracking systems.
milstar: Another important feature is the input voltage full scale range. The harmonic performance of the ADC is so low that the system performance could be badly affected by poor spurious levels on the input driver. This problem is reduced if the ADC can accept a low input voltage. The EV12AS200 has an input voltage range of 500mVpp.
milstar: The AD9625 is the only open-market-available 12-bit, 2-GSPS, A/D converter that simplifies the digital interfacing challenge by integrating two digital-down converters (DDC), two numerically controlled oscillators (NCO) and a configurable JESD204B serial link for the output data. These industry firsts improve usability and functionality by reducing output data rate requirements and simplifying board-level design and layout. Key applications include ultra-wideband RADAR, wideband front-ends for digital storage oscilloscopes and data acquisition platforms. http://redesign.automation.com/product-showcase/analog-devices-releases-ad9625-ad-converter
milstar: AD9625 12-bit A/D Converter Features Exclusive Among Gigasample ADCs Best AC Parametric Performance: 56dB of SNR and 75dBc SFDR up to 1.8GHz input frequency Smallest Form Factor 12x12 mm2 196 BGA 80% smaller than the ADC12D1800RF Higher Levels of Integration, Functionality http://de.slideshare.net/AnalogDevicesInc/ad9625-12bit-2-5-gsps-analogtodigital-converter
milstar: http://www.ll.mit.edu/HPEC/agendas/proc09/Day2/S4_1405_Song_presentation.pdf -------- In order to prevent the spurs and intermods from interfering with small signal detection, the linearity needs to be enhanced to reduce the spur and intermod levels. MIT Lincoln Laboratory has developed the nonlinear equalization (NLEQ) and Time Varying Quantization (TVQ) technologies to enhance linearity of mixed-signal sensor systems. The NLEQ technique can digitally model the ADC nonlinearities and subtract them out from the digitized output to suppress the spur and intermod levels. However, because NLEQ algorithm can only suppress low-order nonlinearities, linearity improvements have often been limited until recently. The new TVQ technology can achieve significantly higher linearity by suppressing high order nonlinearities that the NLEQ technique cannot address. An especially designed additive signal (TVQ signal) is inserted at the input of the ADC. The TVQ signal is designed to minimize the coherent integration of spurs and intermods, including high-order spurs/intermods that are difficult to equalize. The resulting digitized signal mainly contains low-order nonlinearities that are then be attenuated by the NLEQ technique. The preliminary experimental results indicate up to four orders of magnitude higher spur-free dynamic range (SFDR) and intermod-free dynamic range (IFDR) may be possible with the linearity enhancement techniques. This means that sensors would be able to operate properly in environments with a ten thousand times higher interference signals. We believe that many commercial and military applications could benefit from the TVQ/NLEQ technology especially for systems that need to operate in challenging environments. Dr. William S. Song is a senior staff member in the Embedded and Open Systems Group at MIT Lincoln Laboratory. He received his B.S., M.S., and Ph.D. degrees from the Massachusetts Institute of Technology in 1982, 1984, and 1989, respectively. Since his arrival at Lincoln Laboratory in 1990, Dr. Song has been working on high-performance sensor and VLSI signal processor technologies for various applications. He has developed numerous advanced signal processing algorithms, architectures, real-time embedded processors, and sensor array systems. Recently, he has been working on the graph processor, communications processor, linearity enhancement techniques, mixed-signal system on chip, high-throughput low-power VLSI signal processors, and highly digitized wideband sensor arrays. Dr. Song has been the technical director for a number of programs, including the cooperative communication processor, graph processor, wideband linearity enhancement processor, X-band element-level digitized sensor array, receiver-on-chip, space-based radar onboard signal processor, high-dynamic-range digital receiver, adaptive digital beamformer processor, and miniaturized mixed-signal receiver/processor programs. He has also designed a series of high-performance special-purpose signal processor ICs for these applications. His accomplishments include 14 U.S. patents with 1 more pending, 24 invention disclosures, and 28 journal and conference publications. He received MIT Lincoln Laboratory Technical Excellence Award in 2006. He is also an IEEE Senior Member. http://ieeeboston.org/event/receiver-linearity-enhancement-techniques/
milstar: http://www.electronicproducts.com/Videos/Arrow_Product_Insights_Analog_Devices_AD9625_HMC7044_and_ADA4961.aspx video
milstar: With stretch processing we are limited to a range extent that is usually smaller than an uncompressed pulse width. Thus, we couldn’t use stretch processing for search because search requires looking for targets over a large range extent, usually many pulse widths long. --------------------------------------------------- We could use stretch processing for track because we already know range fairly well but want a more accurate measurement of it. We must point out that, in general, wide bandwidth waveforms, and thus the need for stretch processing, is “overkill” for tracking. Generally speaking, bandwidths of 1s to 10s of MHz are sufficient for tracking -------------------------------------- One of the most common uses of wide bandwidth waveforms, and stretch processing, is in discrimination, ------------------------------------------------------------------------------------- where we need to distinguish individual scatterers on a target. Another use we will look at is in SAR (synthetic aperture radar). Here we only try to map a small range extent of the ground but want very good range resolution to distinguish the individual scatterers that constitute the scene. http://www.ece.uah.edu/courses/material/EE710-Merv/Stretch_11.pdf
milstar: 25.2 blocksxema priemnika radara http://jocoleman.info/pubs/papers/SkolnikCh25.pdf Direct Digital Downconversion. If the designer has some flexibility in either the IF center frequency or ADC sample rate, a simplified DDC architecture, direct digital downconversion, can be considered.4,5 If the ADC sample rate is four times the center of the IF band, then the sampling process can also shift the spectrum to baseband, and the NCO and associated multipliers of the general DDC are not needed. In general, direct conversion to baseband is a simple and cost-effective DDC method that can be used when the signal being sampled is always centered at a single frequency. The standard DDC architecture might need to be used when the center frequency of the signal being sampled dynamically changes, which forces the DDC’s LO to change accordingly.
milstar: http://www.ridgetopgroup.com/products/semiconductors-for-critical-applications/instacell-ip-core-library/analog-to-digital/#RGADC-14B-3G-RH Time-interleaved pipeline architecture 500 MS/s to 3 GS/s sampling speed 12-14 bits resolution, programmable (11-12 bits ENOB) SiGe BiCMOS technology Uses 77% less power than commercially available ADCs Two configurable pipeline channels Four programmable operation modes Hard to 1 Mrad TID Hard to 120 MeV-cm2 /mg SEL
milstar: http://www.ridgetopgroup.com/products/semiconductors-for-critical-applications/instacell-ip-core-library/analog-to-digital/#RGADC-14B-3G-RH Time-interleaved pipeline architecture 500 MS/s to 3 GS/s sampling speed 12-14 bits resolution, programmable (11-12 bits ENOB) SiGe BiCMOS technology Uses 77% less power than commercially available ADCs Two configurable pipeline channels Four programmable operation modes Hard to 1 Mrad TID Hard to 120 MeV-cm2 /mg SEL
milstar: http://mil-embedded.com/articles/sige-based-warfare-processing-performance/ SiGe ADC
milstar: http://www.armms.org/media/uploads/5-5_gsps_adc_platform_concept_e2v.pdf In this paper we will introduce a 5Gsps ADC platform for RF and Instrumentation based on programmable interleaving of four fast ADC cores on a single chip.
milstar: http://www.cwcdefense.com/products/cots-boards/io-communication/analog-io/tadf-4300.html 12gsps/ 8bit
milstar: SiGe BiCMOS 0.35 micron 500msps 12 bit 2007 http://www.e2v.com/news/e2v-selects-jazz-semiconductor-for-next-generation-analogue-to-digital-converter-adc-products/
milstar: e2v’s EV12AS350 is set to be the only 12-bit resolution ADC on the market that combines signal digitisation at 5.4GSps, instantaneous bandwidth in excess of 3GHz and latency as low as 26 clock cycles with a noise of -150dBm/Hz. Unlike other ADCs on the market, it will be free of non-harmonic spurs, creating a pure signal for coders to manipulate in a range of demanding applications. http://www.electronicspecifier.com/mixed-signal-analog/next-gen-12-bit-adc-offers-5-4gsps
milstar: Main Features • Single Core ADC Architecture with 12-bit Resolution Integrating a Selectable 1:1 and 1:2 DEMUX • Differential Input Clock (AC Coupled) • 500 mVpp Analogue Input Voltage (Differential Full Scale and AC Coupled) • Noise Floor of –150 dBm/HZ (13-bit ENOB in 10 MHz Bandwidth) • Analogue and Clock Input Impedance: 100Ω Differential • LVDS Differential Output Data • NPR 48.5 dB (Equivalent 9.6 ENOB) • 3 Wire Serial Interface (3WSI) Digital Interface (Write Only) with Reset Signal • ADC Gain, Offset, Sampling Delay for Interleaving Control • No Missing Codes at 1.5 GSps 1st and 2nd Nyquist • Low Latency (< 5 Clock Cycles) -------------------------------------------- • Test Modes • Data Ready Common to the 2 Output Ports • Power Supply: 5.2V, 3.3V and 2.5V (Output Buffers) • Power Dissipation: 3.2W • FpBGA 196 Package (15x15 mm2 ) http://www.e2v.com/resources/account/download-datasheet/1784 The EV12AS200 is a 12-bit 1.5 GSps ADC. The device includes a front-end Track and Hold stage (T/H), followed by an analog encoding stage (Analog Quantizer) which outputs analog residues resulting from analog quantization. Successive banks of latches regenerate the analog residues into logical levels before entering an error correction circuitry and a resynchronization stage followed by a DEMUX with 100Ω differential output buffers. Differential analog input voltage (Full Scale) VIN – VINN 100Ω differential 500 mVpp
milstar: • Noise Floor performance @ 1.5 Gsps / Fin = 1500 MHz, –1 dBFS SNR + 10log (1.5 GHz/2) = 56.5 dB + 10log (750 MHz) = 56.5 dB + 89 dB = 145.5 dBFS/Hz = 144.5 dBc/Hz = –150.5 dBm/Hz Reminder: (ADC Full Scale Input Power: 0.5 Vpp / 100Ω = –5 dBm) http://www.e2v.com/resources/account/download-datasheet/1784 • A noise Floor of –150 dBm Hz corresponds to: • In 750 MHz Bandwidth (1st Nyquist or 2nd Nyquist): 9.1 Bit ENOB (= Full Nyquist region: entire 2nd Nyquist Band) (from SNR = 56.6 dBFS at 1.5 Gsps / Fin = 1490 MHz, –1 dBFS) • In 10 MHz Bandwidth: 13 Bit ENOB ! (from 150 dBm – 10log(10 MHz) = 150 – 70 dB = 80 dB : = 13 Bit ENOB
milstar: Texas Instruments – Industry’s first 16-bit 1-GSPS ADC and highest-density 14-bit ADC (ADS54J60) May 13 2015 http://www.electropages.com/2015/05/texas-instruments-industrys-16-bit-1-gsps-adc-highest-density-14-bit-adc/ ADS54J60 offers more than 3dB better SNR (70 dBFS at FIN=170 MHz) a low noise floor of -159 dBFS/Hz, and spurious-free dynamic range (SFDR) of 86dBc. These enable high spectral purity and the ability to find weak signals in the presence of large, unwanted blockers. 3 – High density: ADS54J54 is 50 percent smaller than competitive ADCs, offering four channels in a 9mm x 9mm package. http://www.ti.com/lit/ds/symlink/ads54j60.pdf 159 dbfs -10log 10mhz = 159 -70 89 dbfs SINAD by fin 170 mhz 1 gsps 7 Detailed Description 7.1 Overview The ADS54J60 is a low-power, wide-bandwidth, 16-bit, 1.0-GSPS, dual-channel, analog-to-digital converter (ADC). Designed for high signal-to-noise ratio (SNR), the device delivers a noise floor of –159 dBFS/Hz for applications aiming for highest dynamic range over a wide instantaneous bandwidth. The device supports the JESD204B serial interface with data rates up to 10.0 Gbps, supporting two or four lanes per ADC. The buffered analog input provides uniform input impedance across a wide frequency range while minimizing sample-and-hold glitch energy. Each ADC channel optionally can be connected to a wideband digital down converter (DDC) block. The ADS54J60 provides excellent spurious-free dynamic range (SFDR) over a large input frequency range with very low power consumption. The ADS54J60 has a thermal noise of approximately 71.1 dBFS and an internal aperture jitter of 145 fs. The SNR, depending on the amount of external jitter for different input frequencies, is shown in Figure 124.
milstar: 2007 http://www.eetimes.com/document.asp?doc_id=1272390 One of the main factors limiting the input frequencies which can be sampled is the development of circuits to drive the input to today's A/D converters, not just the limitations of the converters themselves. Input swings of 2 VPP are typical for high-performance pipeline converters, ---------------------------------------------------------------------------- and this strain is placed directly on the input buffer circuit. The input buffer usually consists of an op amp driving the full input swing to maximize SNR performance. But silicon-based op amps tend to have limited performance at higher IFs. These limitations directly affect the overall performance of the system. Recent developments in silicon germanium material (SiGe) have allowed amplifier operating frequencies to push beyond silicon limitations. Currently, amplifiers are available that are designed to operate up to and beyond 350 MHz. SiGe also has been used in some of the highest-performing A/D converters and allows building a unity-gain buffer into the converter in front of the sample-and-hold circuit. This provides a high-impedance load to the external buffer stage, allowing easy implementation of buffer circuits with transformers when dc signals are not needed, or with amplifiers when dc is required.
milstar: The ADC12J4000 device is based on an ultra high-speed ADC core. The core uses an interleaved calibrated folding and interpolating architecture -------------------------------------------------------------- that results in very high sampling rate (4 gaps) , very good dynamic performance, and relatively low-power consumption. ne 1 adc http://www.ti.com/lit/ds/symlink/adc12j4000.pdf
milstar: Figure 80 uses a 1:2 impedance transformer to provide the 100 Ω input impedance of the ADA4961 with a matched input. The open collector outputs of the ADA4961 are biased through the two 560 nH inductors. The two 0.1 μF capacitors on the outputs decouple the 5 V inductor voltage from the input common-mode voltage of the ADA4961. The two 50 Ω resistors in parallel with the 100 Ω input impedance of the AD9625 provide the 50 Ω load to the ADA4961, whose gain is load dependent. The 2 nH inductors and the 1.5 pF internal capacitance of the AD9625 constitute a 1 GHz low-pass filter to −1 dB. The two 10 Ω isolation resistors suppress any switching currents from the AD9625 sample-and-hold circuitry. The circuit depicted in Figure 80 provides variable gain, isolation, filtering and source matching for the AD9625. By using this circuit with the ADA4961 in a gain of 15 dB (maximum gain) an SNRFS of 55 dB and an SFDR performance of 77 dBc are achieved with a 1 GHz input as shown in Figure 80. http://www.analog.com/media/en/technical-documentation/data-sheets/AD9625.pdf The AD9625 architecture includes two DDCs, each designed to extract a portion of the full digital spectrum captured by the ADC. Each tuner consists of an independent frequency synthesizer and quadrature mixer; a chain of low-pass filters for rate conversion follows these components. Assuming a sampling frequency of 2.500 GSPS, the frequency synthesizer (10-bit NCO) allows for 1024 discrete tuning frequencies, ranging from −1.2499 GHz to +1.2500 GHz, in steps of 2500/1024 = 2.44 MHz. The low-pass filters allow for two modes of decimation. • A high bandwidth mode, 240 MHz wide (from −120 MHz to +120 MHz), sampled at 2.5 GHz/8 = 312.5 MHz for the I and Q branches separately. The 16-bit samples from the I and Q branches are transmitted through a dedicated JESD204B interface. • A low bandwidth mode, 120 MHz wide (from −60 MHz to +60 MHz), sampled at 2.5 GHz/16 = 156.25 MHz for the I and Q branches separately. The 16-bit samples from the I and Q branches are transmitted through a dedicated JESD204B interface.
milstar: Improve receiver noise figure A high-speed analog-to-digital converter (ADC) typically has the largest noise figure of all components in the receiver signal chain. Its contribution to the system noise figure can be reduced greatly by adding more gain (with a low noise figure) upfront using low-noise amplifiers (LNAs). However, this method cannot be used in a blocking scenario. In the presence of a large in-band interferer or jammer that can’t be filtered out, the gain in the signal chain must be reduced in order to avoid saturation of the ADC input. http://www.microwavejournal.com/ext/resources/whitepapers/2015/May-2015/HS-ADC-never-has-enough-SNR_FINAL.pdf?1431868975 herefore, the only way to really improve the receiver noise figure is to improve the noise floor by using a data converter with a better signal-to-noise ratio (SNR), as shown in the example in Figure 2. For comparison, the SNR of the ADS42JB69 is almost 3 dB better; however, the Nyquist zone of the ADS54J60 is three times larger. As a result, its NSD is 3.1 dB better and is approaching –160 dBFS/Hz, which is a very good value for a high-speed pipeline ADC. Together with the slightly smaller input full-scale signal swing, the noise figure of the ADS54J60 is 3.5 dB better than the ADS42JB69.
milstar: What determines ADC thermal noise? The ADC’s noise floor is determined by three different noise contributors: quantization, thermal noise and clock jitter. The quantization noise impact (which originates from the rounding error of the least significant bit [LSB]) is usually very small, as the designer increases the ADC output resolution accordingly. For example, the quantization noise of a 16- bit output resolution is – (16 * 6.02 + 1.76) ~ –98 dBFS. So the quantization noise has minimal impact on the SNR of a 16-bit ADC. Clock jitter primarily affects the ADC’s SNR at higher input frequencies with a full- power input signal. Sensitivity testing is often performed with a smaller (backed- off) input signal, where clock jitter noise is not a factor. Hence, the ADC noise floor is solely determined by thermal noise.
milstar: For high-dynamic-range multiband receivers, the ADS54J60 delivers one of the widest bandwidths of 500 MHz with one of the lowest noise floors, approaching –160 dBFS/Hz. http://www.microwavejournal.com/ext/resources/whitepapers/2015/May-2015/HS-ADC-never-has-enough-SNR_FINAL.pdf?1431868975
milstar: http://www.ti.com/lit/wp/slyy068/slyy068.pdf Direct RF conversion: From vision to reality
milstar: Теоретически возможные величины ЭПР некоторых перспективных кораблей для длины волны 10 см = 3 Ghz S-Band (Aegis SPY-1) авианосец средняя > 25 000 м2,промежуточный КУ 900–1000 м2 эсминец ,фрегат 1 500–4 000 м2 ,промежуточный КУ 200 -300 м2 http://vpk-news.ru/articles/8474 Dlja srawneniya B-2 Spirit - 0.75 м2 ------------------------ NIIP Irbis-E s apperturoj diametrom 900mm ,srednej moschnostju 5 kwt/impulsnoj = 20 kwt dalnost dlja EPR 0.01 kw.metr = 50nmi ili 90 km dlja EPR 2.56 kw.metra =360 km http://www.ausairpower.net/APA-Flanker.html ------------------------------------------- Баллистическая ракета средней дальности Pershing-2 (MGM-31C) Система управления дополнялась системой наведения ГЧ на конечном участке траектории по радиолокационной карте местности (система RADAG). Такая система на баллистических ракетах ранее не применялась. Комплекс командных приборов располагался на стабилизированной платформе, помещенной в цилиндрический корпус, и имел свой электронный блок управления. Работу системы управления обеспечивал бортовой цифровой вычислстельный комплекс, размещенный в 12 съемных модулях, и защищенный алюминиевым корпусом. Система RADAG состояла из бортовой радиолокационной станции и коррелятора. РЛС экранировалась и имела два антенных блока. Один из них предназначался для получения радиолокационного яркостного изображения местности. Другой - для определения высоты полета. Изображение кольцевого типа под головной частью получалось за счет сканирования вокруг вертикальной оси с угловой скоростью 2 об/сек. Четыре эталонных изображения района цели для разных высот хранились в памяти ЦВМ в виде матрицы, каждая ячейка которой представляла собой радиолокационную яркость соответствующего участка местности, записанную двухзначным двоичным числом. К аналогичной матрице сводилось полученное от РЛС действительное изображение местности, при сравнении которого с эталонным можно было определить ошибку инерциальной системы. Полет головной части корректировался исполнительными органами - реактивными соплами, работавшими от баллона со сжатым газом вне атмосферы, и аэродинамическими рулями с гидравлическим приводом при входе в атмосферу http://rbase.new-factoria.ru/missile/wobb/pershing_2/pershing_2.shtml -------------------------------------------------------------------------------- Комплекс П-800 / 3К55 Оникс / Яхонт - SS-N-26 STROBILE Система управления и наведение - активно-пассивное РЛ-наведение, на ракете установлены активная РЛС ГСН и бортовая БЦВМ. Дальность обнаружения цели ГСН в активном режиме - 50 км (по одним данным) Дальность обнаружения цели класса "крейсер" ГСН в активном режиме - 75-77 км ============================== Дальность обнаружения цели ГСН в активном режиме минимальная - 1 км Сектор обнаружения ГСН - +-45 градусов Диаметр ракеты -700 mm После обнаружения и захвата цели ГСН ракеты, ГСН выключается и ракета "ныряет" под нижнюю границу зоны ПВО цели и управляется инерциально. После выхода за линию радиогоризонта ГСН вновь включается ГСН. Распределение целей происходит на первом этапе работы ГСН (на высоте). При групповом старте ПКР на первом этапе группа ракет перераспределяет цели по определенному алгоритму, исключая возможность поражения одной цели несколькими ракетами (если это не главная цель). Ракеты запрограммированы на совершение противоракетных маневров. В память бортовой БЦВМ заложены электронные "портреты" основных кораблей потенциальных противников и логика определения построения корабельных ордеров для выбора главной цели. http://militaryrussia.ru/blog/topic-92.htm ----------------------------------------------- Противокорабельная ракета 3М-54Э / 3М-54Э1 На дистанции около 30-40 км от цели ракета делает "горку" и происходит включение АРГС -54 (см.схему). После обнаружения и захвата цели головкой самонаведения у ракеты 3М-54Э происходит отделение второй ступени и начинает работать третья боевая твердотопливная ступень, развивающая скорость до 1000 м/с. На конечном участке полета протяженностью около 20км боевая ступень ракеты 3М-54Э снижается на высоту до 10м. У двухступенчатой ПКР 3М-54Э1 полет на всей траектории происходит на дозвуковой скорости, а непосредственно перед целью выполняется специальный зигзагообразный противоракетный маневр. Количество одновременно обстреливаемых целей -2, количество ракет в залпе - 8, интервал между пусками - 5-10с. Бортовая система управления ракет 3М-54Э / 3М-54Э1 построена на базе автономной инерциальной навигационной системы АБ-40Э (разработчик - Государственный НИИ Приборостроения). Наведение на конечном участке траектории осуществляется при помощи помехозащищенной активной радиолокационной головки самонаведения АРГС-54. АРГС-54 разработана фирмой "Радар-ММС" (г.Санкт-Петербург) и имеет максимальную дальность действия до 65км. Длина головки - 70см, диаметр - 42см и вес - 40кг. АРГС-54 может функционировать при волнении моря до 6 баллов. http://rbase.new-factoria.ru/missile/wobb/3m54e1/3m54e1.shtml ---------------------------------------- Моноимпульсная головка самонаведения ракеты "Яхонт" http://rbase.new-factoria.ru/missile/wobb/jakhont/jakhont-head.shtml Головка самонаведения (ГСН) предназначена для поиска и обнаружения морских и наземных целей в условиях радиоэлектронного противодействия, селекции ложных целей, выбора цели по заданным критериям, захвата и сопровождения выбранной цели, выработки координат цели и выдачи их в систему автопилотирования бортовой аппаратуры системы управления (БАСУ) противокорабельной крылатой ракеты (ПКР) «Яхонт». ГСН выполняет указанные выше действия в любых погодных условиях при волнении моря до 7 баллов включительно. Состав аппаратуры ГСН представляет собой бортовой двухканальный активно-пассивный радиолокатор со сложным широкополосным когерентным сигналом с фазо-кодовой манипуляцией по случайному закону как в режиме обзора, так и в режиме сопровождения цели при работе в активном режиме. ГСН осуществляет перестройку частотно-временных параметров, обладает высокой помехозащищенностью по отношению к различным видам активных помех, уводящих по дальности и угловым координатам, и пассивных помех типа дипольных облаков и уголковых отражателей, адаптивна к помеховой обстановке и условиям применения. ГСН построена по модульному принципу: антенна, передатчик, приемник, устройство обработки информации (см.структурную схему). ГСН имеет средства встроенного самоконтроля. В ГСН воплощены новейшие научно-технические достижения ЦНИИ «Гранит» и других предприятий военно-промышленного комплекса России: функциональная СВЧ-микроэлектроника на базе тонко- и толстопленочной технологии; современная микропроцессорная техника и микро-ЭВМ; прогрессивные конструкции и технологические процессы изготовления; высокоэффективная система питания. Оригинальные решения, используемые в ГСН запатентованы. Все это позволило получить высокую степень интеграции при минимальных объемах аппаратуры, малое энергопотребление и низкую трудоемкость изготовления. Основные тактико-технические характеристики Дальность обнаружения цели в активном режиме не менее 50 км Максимальный угол поиска цели ± 45° Время готовности к работе с момента включения не более 2 мин Потребляемый ток по цепи 27В не более 38А Масса 85 кг -------------------------------------- АРГС для ракеты РВВ-АЕ http://www.mnii-agat.ru/expo/334/prod_2845_r.htm Многофункциональная моноимпульсная доплеровская активная радиолокационная головка самонаведения для ракеты РВВ-АЕ класса «воздух-воздух» обеспечивает: - поиск, захват и сопровождение цели по целеуказанию от инерциальной системы управления ракеты; - измерение угловых координат и угловых скоростей цели и скорости сближения ракета - цель и передача их в ракету для формирования сигналов управления. Режимы работы: - активный режим, полностью автономный ("пустил-забыл"), использующий только предварительное целеуказание, без радиолокационнной поддержки в полёте; - режим инерциального наведения с радиокоррекцией и активным наведением на конечном участке полета. Тактико-технические характеристики: 1. Состав: - управляемый координатор с антенной - передающий канал - приемный канал - бортовая вычислительная система 2. Тип системы наведения: - инерциальное наведение с радиокоррекцией и активное самонаведение 3. Канал радиокоррекции и АРГС обеспечивает пуск ракеты РВВ-АЕ с самолета типа МИГ-29 в ППС на максимальной дальности - до 80 км. 4. Время готовности после предварительного включения в течение 2 мин. - не более 1с 5. Длина (без обтекателя), мм - 604 6. Масса (без обтекателя), кГ - не более 16 7. Диаметр, мм - 200 Сотрудничество возможно в плане приобретения и испытаний ракеты РВВ-АЕ. По желанию Заказчика параметры АРГС могут изменяться.
milstar: FIGURE 2 ASBM KILL RADIUS [url=http://www.chinasecurity.us/pdfs/others/Hagt&Durnin.pdf]http://www.chinasecurity.us/pdfs/others/Hagt&Durnin.pdf[/url] Source: Chen Haidong et al., “Study for the Guidance Scheme of Reentry Vehicles Attacking Slowly Moving Targets.” Another source draws the conclusion—using a different simulation—that the warhead could have a kill radius of one hundred kilometers once terminal guidance was engaged.36 In a discussion in Naval and Merchant Ships, Dong Lu calculates the maximum distance at which the basic radar terminal guidance of a similar missile system, the retired U.S. Pershing II, could detect a carrier that had maneuvered for fifteen minutes, given a scanning height for the missile’s radar of nineteen kilometers.37 Still, a number of unique technical obstacles remain, such as the materials needed to protect sophisticated guidance systems during reentry;39 the ability to function in an environment of higher speed and more severe temperature dynamics than in earlier applications;40 and the ability to distinguish a target at unusual angles of attack at the distances required for reentry.41 A number of publications view U.S. missile defenses as a primary concern for the ASBM in its terminal phase as well as midcourse. Some believe that the ASBM will have to slow down considerably in order to locate and maneuver to the carrier, making it a much more manageable problem for missile defenses.42 Others see the difficulties in fending off electronic jamming and measures against active-radar terminal seekers.
milstar: The angle tracking receiver presented in this paper has a high dynamic range of 100 dB with minimum SNR requirement of 3 dB. The configuration of this monopulse angle tracking receiver is given in ref [2]. High dynamic range is obtained by converting angular information into frequency domain whereas phase and gain matching is obtained by providing the gain after combining the sum and difference signals. http://sensorsresearchsociety.org/Sensors2007CD/CP_50.pdf
milstar: A High Dynamic Range Receiver for the Radar Open System Architecture http://highfrequencyelectronics.com/Archives/May08/HFE0508_Cannata.pdf Summary High-speed RF signal capture with wide dynamic range signals is readily achievable with today's high-speed ADCs. With careful design followed by the appropriate digital sig- nal processing, i it is possible to capture and recreate signals with dynamic ranges in excess of 100 dB. --------------------------------------------------------------------------------------------- http://highfrequencyelectronics.com/Archives/Sep08/HFE0908_S_Crean.pdf Symtx Inc. has implemented a dual ADC scheme to increase digitizer dynamic range as shown in Figure 3. The design uses a high-gain channel to process low-level sig- nals and a low-gain channel to process high-level signals, with simultaneous sampling of both channels in parallel. The gain difference between the high-level and low level ADCs is compensated with an appropriate n-bit left shift to give the correct scaling. A DSP after the two ADCs then selects the correct ADC output, adjusts for gain, and merges the two to create a 20-bit word with the desired dynamic range.
milstar: PROCESSING IN CLUTTER Background The ultimate goal of the antiship missile seeker is to generate adequate target range and angle estimate inputs to the guidance system to enable the ASM to impact the ship. Signal processing is applied to the data to better detect the ship return and to extract the measurements. Examples of this signal processing include 1. range compression, 2. Doppler processing, 3.detection, 4.target discrimination, 5. and monopulse angle estimation. http://www.dtic.mil/cgi-bin/GetTRDoc?AD=ADA430023
milstar: Эффективная площадь рассеяния в диапазоне Х конический боевой блок = 0.01 квадр .метра THAAD Средняя(1) мощность = 81 киловатт 25344*3.2 ватта коэффициент усиления антенны = 103 000 = 41 db Шумовая температура = 400° K эффективность апертуры антенны = 0.8 площадь антенны = 9.2 m^2 длина импульса = 1 миллисекунда коэффициент заполнения =0.2 PRF = 200 Сигнал/шум обнаружение = 20 Сигнал/шум дискриминация = 100 дальность обнаружение = 870 километров дальность дискриминация =580 километров ####### Сдвоенная THAAD 18.4 m^2,162 киловатт дальность обнаружение = 1460 километров дальность дискриминация =970 километров http://mostlymissiledefense.com/2012/09/21/ballistic-missile-defense-radar-range-calculations-for-the-antpy-2-x-band-and-nas-proposed-gbx-radars-september-21-2012/ Данные по THAAD для углов элевации 30 ° и более ,При углах элевации ниже 10° дальность падает в 4-5 раз . Атака в группе , подрыв ядерного блока , заход на цель на фоне вспышки остальными резко повышает шумовую температуру радара
milstar: http://www.ep.liu.se/ecp/008/posters/019/ecp00819p.pdf SUMMARY In this paper, we evaluate a new design of a previously presented (second order) tunable active X-band MMIC filter. By using a two-stage low noise amplifier in each filter section a higher filter gain and selectivity as well as a lower filter noise figure can be achieved at the expense of a smaller filter tuning range. The filter is tunable to eight different center frequencies between 7.6-8.6GHz. Typical measured data for all eight tuning states show a maximum gain that varies between 13-26dB, a 4-5dB noise figure and a spurious-free dynamic range of 58-67dB. The presented filter could potentially be utilized as an important building block to realize agile compact on-chip receiver front-ends for future adaptive X-band radar array antennas, for example. INTRODUCTION A low vulnerability to jamming signals due to electronic warfare or electromagnetic interference, for example, is of prime importance in modern radar systems. One way to achieve this is to use a frequency hopping radar where the transmitter and the receiver jump in a pseudo-random like way between different selected frequencies. To further reduce the vulnerability to jamming signals adaptive methods and digital beamforming can be adopted [1]. In future adaptive array antennas the number of transmit/receive (T/R) modules required is anticipated to be as high as several hundreds or more. To be able to realize such multi-channel radar systems in a cost-effective way size and cost of each T/Rmodule should be minimized. As a consequence of this, increased interest has been focused on the possibility of using tunable narrow-band active monolithic microwave integrated circuit (MMIC) filters to reduce the vulnerable bandwidth of frequency hopping radar receivers [2]. Compared with using a fixed frequency bandpass filter, a tunable filter may reduce the number of down-converting stages required in an agile receiver by allowing a greater down-conversion step to be made. Rejection of interfering signals that, for example, may occur at the receiver image frequency (fimage=fRF±2fIF where fRF and f IF denote the radar frequency and the intermediate frequency of the receiver, respectively) should be high enough to minimize the effect of jamming. In this paper, we focus on active filters that may be used in receiver front-ends of adaptive X-band (8-12GHz) antennas. Typical requirements for such filters can be found in [3] (see Table 1). Below, we evaluate a re-design of a tunable X-band MMIC filter originally presented in [4]. Compared with results obtained in [4], an improved performance in terms of higher gain and selectivity as well as lower noise figure is achieved. Center frequency gain (G) > 10dB Noise figure (NF) < 5 dB Input third order intercept point (IIP3) ≥ 0 dBm Spurious-free dynamic range (SFDR) ≥ 113 dB/Hz2/3 (≥ 64dB for a noise bandwidth B= 20MHz) Table 1: Typical requirements for active filters if used in receivers of adaptive X-band radar antennas.
milstar: 5.12 MULTIFUNCTIONAL RADAR SYSTEMS FOR FIGHTER AIRCRAFT 1.Real beam map 0.5 -10 mgz 2.Doppler beam sharp 5-25 mgz 3. SAR 10 -500 mgz 4.A-S range 1-50 mgz -------------------------- 5.PVU 1-10 mgz 6.TF/TA 3-15 mgz 7.Sea surface search 0.2 -500 mgz 8.Inverse SAR 5-100 mgz 9. GMTI 0.5-15 mgz 10.Fixed target track 1-50 mgz 11.GMTT 0.5 -15 mgz 12.Sea Surface track 0.2-10 mgz ------------------------------------ 13.Hi power Jam 1-100 mgz 14.CAl/A.G.C 1-500 mgz 15A-S data link 0.5-250 mgz
milstar: http://www2.l-3com.com/eti/downloads/aoc_paper_placard.pdf Affordable High Performance Broadband Scanning Multi-Beam Antenna/Amplifier Subsystem
milstar: Description The ADS54J60 is a low-power, wide-bandwidth, 16-bit, 1.0-GSPS, dual-channel, analog-to-digital converter (ADC). Designed for high signal-to-noise ratio (SNR), the device delivers a noise floor of –159 dBFS/Hz for applications aiming for highest dynamic range over a wide instantaneous bandwidth. The device supports the JESD204B serial interface with data rates up to 10 Gbps, supporting two or four lanes per ADC. The buffered analog input provides uniform input impedance across a wide frequency range while minimizing sample-and-hold glitch energy. Each ADC channel optionally can be connected to a wideband digital down-converter (DDC) block. The ADS54J60 provides excellent spurious-free dynamic range (SFDR) over a large input frequency range with very low power consumption. The JESD204B interface reduces the number of interface lines, allowing high system integration density. An internal phase-locked loop (PLL) multiplies the ADC sampling clock to derive the bit clock that is used to serialize the 16-bit data from each channel. Features 16-Bit Resolution, Dual-Channel, 1-GSPS ADC Noise Floor: –159 dBFS/Hz Spectral Performance (fIN = 170 MHz at –1 dBFS): SNR: 70 dBFS NSD: –157 dBFS/Hz Price 706 $ P cons -2.7 watt V pp -1.9 v http://www.ti.com/product/ADS54J60 Data latency(1): ADC sample to digital output 134 input clock cycles ##############################################
milstar: http://www.analog.com/media/en/technical-documentation/data-sheets/AD9625.pdf ad9625 2.5-2.6 gsps 12 bit Vpp -1 v 100 ohm ,1.5 pf Pdiss -4 watt Fin 1 ghz ,ENOB = 9.1 bit ,SFDR -79 dbc (!) FAST DETECT OUTPUT (FD) Latency Full 82 Clock cycles ######################### Pipeline latency 226 glock cycles aperture delay -200 ps
milstar: ADC12D1800RF http://www.ti.com/lit/ds/symlink/adc12d1800rf.pdf Vpp -0.8-1 v Cin -1.6 pf Rin -100 ohm P consump -4.7 watt Fclk -1.8 ghz aperture jitter -0.2 ps Latency t lat -34 sampling clock cycles -------------------------------------------
milstar: Low latency ADC 3 stage pipeline TI 12-Bit, 1-GSPS Analog-to-Digital Converter http://www.ti.com/lit/ds/symlink/ads5400.pdf Latency 7.5-8.5 cycles Apperture delay- 250 ps Jiter -125 fs ------------------------- E2V folding interpolation SiGe 0.18 micron 200 ghz pprocess http://www.e2v.com/resources/account/download-datasheet/1784 EV12AS200ZPY 12-bit 1.5 Gsps ADC The EV12AS200 works in fully differential mode from analog inputs through digital outputs. It operates in the first Nyquist zone up to L-Band. Rin =100 ohm,0.3 pf Pin -0.5v pp latency -5 cycles apperture delay -75 ps jitter -100 fsrms output data pipeline delay -4-5 cycles TPD -Number of clock cycles between the sampling edge of an input data and the associated output data being made available, (not taking in account the TOD). (TOD) Digital data Output delay Delay from the rising edge of the differential clock inputs (CLK, CLKN) (zero crossing point) to the next point of change in the differential output data (zero crossing) with specified load. (TDR) Data ready output delay Delay from the falling edge of the differential clock inputs (CLK, CLKN) (zero crossing point) to the next point of change in the differential output data (zero crossing) with specified load.
milstar: military product http://www.appliedradar.com/Datasheets/AR8005.pdf AR8005 Four Channel 1.5 GSPS 8-Bit ADC Single Mezzanine Module The AR8005 ADC chipset allows for either baseband or second Nyquist band real-time sampling of analog IF or RF signals with over 500 MHz of instantaneous bandwidth and 7.5 effective bits. A single onboard PLL clock is used to clock all four ADC channels
milstar: An additional advantage of SiGe-based devices is their low latency, an important feature for bandwidth-sensitive EW applications. ---------------------------------------------------------------------------------------- http://mil-embedded.com/articles/sige-based-warfare-processing-performance/ The new SiGe-based generation of ADCs is delivering the next big performance leap, doubling bandwidth speeds up to 12 GSps. For EW applications, the benefit is straightforward: The higher sample rates and associated bandwidth ensure better spectrum coverage and improved Probability Of Intercept (POI) for signals of interest. In addition, the performance of these 8-bit parts surpasses off-the-shelf 10-bit ADCs in terms of Spurious Free Dynamic Range (SFDR). Typically, a first pass of the spectrum segment is done at high bandwidth to pull in as much data as possible to obtain areas of interest to analyze, after which a higher-resolution, lower-bandwidth solution is leveraged to focus on specific targets. As warfighters see a far greater range of the spectrum, more lives are saved and mission success probability is increased because of faster, more accurate identification of threats and improved response options. An example of an OpenVPX board that delivers the latest generation of devices is Curtiss-Wright’s rugged CHAMP-WB-DRFM 6U card set, combining a Tektronix TADF-4300 module featuring a SiGe-based 12.5 GSps 8-bit ADC and a 12 GSps 10-bit DAC (Figure 1), on a Xilinx Virtex-7 FPGA-based 6U VPX card, the CHAMP-WB.
milstar: This new offering uses an analog-to-digital converter (ADC) from Tektronix that samples at 12 GSamples/s to digitize a bandwidth of 6 GHz. This single-board solution also features a 12-GSamples/s digital-to-analog converter (DAC)at its output, and a Virtex-7 field-programmable gate array (FPGA) from Xilinx that can receive or source data at 12 GSamples/s. The CHAMP-WB-DRFM VPX board consists of Curtiss-Wright’s CHAMP-WB baseboard that contains the FPGA supported by 8 GB of DDR3L SDRAM and the TADF-4300 Enhanced FMC mezzanine card that contains the ADC and DAC that together form the CHAMP-WB-DRFM (see table). http://defenseelectronicsmag.com/systems-amp-subsystems/single-board-captures-digitizes-dc-6-ghz Using the CHAMP-WB-DRFM as the core conversion and processing portion of a digital RF memory (DRFM) in a fighter aircraft as an example, the analog signal from an antenna or downconverter is directly digitized by the ADC on the TADF-4300 and sent via LVDS to the FPGA. Customer-supplied algorithms resident in the FPGA then scour the wideband signal capture stream to find the comparatively narrowband signals from an enemy radar.
milstar: Using the CHAMP-WB-DRFM as the core conversion and processing portion of a digital RF memory (DRFM) in a fighter aircraft as an example, the analog signal from an antenna or downconverter is directly digitized by the ADC on the TADF-4300 and sent via LVDS to the FPGA. Customer-supplied algorithms resident in the FPGA then scour the wideband signal capture stream to find the comparatively narrowband signals from an enemy radar. These cards support commercial applications such as direct RF digitization, ground-penetrating radar (GPR) and coherent optical applications, as well as enabling deployed defense and aerospace, sense & response applications that require wideband capability and low latency, such as DRFM, EW, Signal Intelligence (SIGINT), and Electronic Counter Measures (ECM). http://vita.mil-embedded.com/news/curtiss-wright-electronic-warfare-applications/ The TADF-4300 module supports sampling in the 2nd nyquist zone, to analyze signals up to 8 GHz and provides sub-30 ns latency for the ADC and sub 10ns for the DAC. Spurious Free Dynamic Range varies over frequency, and is >58 dB up to 3 GHz and decreases to 45 dB from 3 GHz to 6 GHz signal input frequency. ENOB varies linearly from 7.2 at low frequency, 6.5 at 3 GHz and 6.2 at 6 GHz.
milstar: For example, for the stressing mission in the electronic warfare (EW), advanced electronic support measure (ESM) receivers are needed to meet the specific requirements and are expected to have the characteristics of broad instantaneous bandwidth (>1 GHz), wide spatial field-of-view, simultaneous signal processing capability, and good sensitivity and dynamic range [6]. Some limitations exist in traditional ESM receivers and need to be overcome. Those limitations include high cost, large physical size, limited programmable flexibility resulting from fixed analog hardware architecture, and analog components’ tendency to drift with time and temperature. To mitigate those problems, pushing the ADC closer to the antenna and eliminating as many analog components as possible is a trend for the design of next-generation ESM receivers. The ADC that can meet the requirements of this ESM receiver should have the capability of sampling the input signal with bandwidth greater than 3 GHz and achieving a dynamic range larger than 60 dB (> 10 bits) file:///C:/Users/gast/Downloads/li_xiangtao_200808_phd.pdf Table 2: Key Specifications of SiGe HBT (npn) BiCMOS Technologies Offered by IBM Microelectronics
milstar: Ridgetop’s radiation-hardened programmable SiGe analog-to-digital data converter (ADC) has fast digitization with extremely high linearity and dynamic range to achieve system performance targets. In many applications, with the added requirement of radiation hardness and low power, the ADC is a critical chokepoint that must meet demanding standards. Accordingly, Ridgetop’s ADC is highly linear with an INL and DNL of no more than ±0.5 LSB, an operating temperature range of at least -10 to 80 °C, a very high effective number of bits (ENOB) of 11.0, and a total ionizing dose (TID) rating of 1 Mrad. The ADC employs an innovative time-interleaved pipeline architecture and is based on the advanced silicon-germanium (SiGe) bipolar complementary metal oxide semiconductor (BiCMOS) General Description ■ Time-interleaved pipeline architecture ■ 500 MS/s to 3 GS/s sampling speed ■ 12-14 bits resolution, programmable (11-12 bits ENOB) ■ SiGe BiCMOS technology ■ Uses 77% less power than commercially available ADCs technology, providing an effective number of bits more than 2 bits higher (ENOB = 11.0 bits) than the best commercially available 3 GS/s ADC. http://www.ridgetopgroup.com/wp-content/uploads/2015/06/PB_RGADC-14B-3G-RH.pdf
milstar: A single-core architecture also has advantages in terms of latency. Fore examples, latencies as low as 3 clock cycles as found with the EV12AS200 [2] are very useful in applications such as EW and tracking systems. ######## http://www.embedded.com/print/4370321
milstar: folding -interpolation ADC по русски КМОП-АЦП со складывающей (folding) архитетурой, которая... https://docviewer.yandex.ru/?url=http%3A%2F%2FCyberLeninka.ru%2Farticle%2Fn%2Fvysokoskorostnoy-bezkondensatornyy-kmop-atsp-s-interpoliruyuschimi-zaschelkami-i-reversiruemym-taktirovaniem.pdf&name=vysokoskorostnoy-bezkondensatornyy-kmop-atsp-s-interpoliruyuschimi-zaschelkami-i-reversiruemym-taktirovaniem.pdf&lang=ru&c=568e58d6ede3&page=1
milstar: Simplify the Routing Multi-gigasample converters with 10-, 12-, or 14-bit resolution generate lots of output data, and in a hurry. The use of low-voltage differential-swing (LVDS) data could require 30 parallel lanes of 1-Gbit/s data for a 2.5-Gsample/s, 12-bit ADC. Handling 30 differential LVDS pairs per ADC can be challenging to route and maintain matched lengths on a system layout. Equivalent data can be sent with only six or eight differential lanes using JESD204B, a high-speed serializer/deserializer (SERDES) standard designed specifically for converter interfaces. JESD204B provides a means to output data at high speeds on fewer data lines without the matched timing board complexities of many high-speed LVDS lanes. Since the data sent over JESD204B is framed, based on an embedded clock and control characters, the routing of the lower-count serial lanes is much more forgiving of timing skew than LVDS (Fig. 2). This removes the need to spend countless hours working to tweak output timing on every I/O of the system PCB. http://electronicdesign.com/analog/gigasample-adcs-promise-direct-rf-conversion Over-Range Detection Adaptive gain algorithms are important in terms of adjusting the amplitude of an analog input signal, since a saturated ADC input essentially makes the system blind in its ability to decipher signals. Ideally, the gain adaptation feedback loop should be as fast as possible. Whether the high-speed ADC output is LVDS-based or uses JESD204B, the added latency of this digital output often can be too long to wait to receive the saturated data, detect the issue, and react to the condition. One solution to this issue is to use a variable-level comparison within the ADC core itself and directly send an immediate output flag upon occurrence of an over-range condition. This technique bypasses the latency of the longer back-end output stage, which shortens the feedback time to the amplifier, allowing for a faster adaptive gain cycle. In addition to this “fast over-range detection” output, the over-range samples can be appended with alert bits, using the JESD204B interface, to let downstream system processing make appropriate decisions about the data. For high-sample-rate systems that don’t need to observe a large frequency spectrum, digital downconversion (DDC) allows a sub-sampling and filtering strategy for decimating the amount of data output from the gigasample-per-second ADC. Downstream processing then observes a smaller portion of the frequency spectrum.
milstar: Data Compression in Radar Systems Introduction An application note describing an efficient method for real time compression of digital data and its application to radar systems Problem One of the most significant developments in radar technology since its first deployment over seven decades ago has been the conversion from analog (RF) to digital for signal processing, transfer, and storage. Solid state technology with digital processing, ultrafast analog to digital converters, commercial microprocessors, digital signal processing (DSP) chips, field-programmable gate arrays (FPGAs), and high speed digital networking have provided the capability of handling radar signal processing in the digital realm. Digitization has led to increasingly fast and efficient processing, broad new opportunities for offering radar sensor information on the tactical internet, as well as innovative ways to display radar information. In addition, multifunctional radar systems are becoming commonplace, increasing the need for sophisticated and powerful data management strategies. With dynamic range and sampling rates on the rise, powerful algorithms demanding more and accurate data, and system architectures becoming increasingly sophisticated, the problems of data bandwidth limitations and storage bottlenecks have come to the forefront of many system designs. These bandwidth issues have the potential to limit system performance if not managed properly. Solution: Real-time data compression Moog is a supplier of high-bandwidth slip rings, fiber optic rotary joints, positional feedback devices, and sophisticated sub-systems for radar (both ground-based and airborne) systems. Samplify®, Inc. is a company that has developed an efficient method for compressing sampled analog signals in real time http://www.globalspec.com/MoogComponents/REF/Note_230_DataComRadar.pdf
milstar: DRFM-Modulator for HRR-Jamming http://ftp.rta.nato.int/public//PubFullText/RTO/MP/RTO-MP-SET-080///MP-SET-080-P07.pdf ABSTRACT The Digital RF Memory (DRFM) is a key component in modern radar jamming systems. To introduce false targets in a High-Range-Resolution (HRR) radar and other high-resolution imaging radars, a new generation DRFM-system is being developed with far better range resolution and modulation properties. The DRFM also needs better performance in the D/A-converter than in the systems used today, because of the high fidelity jamming signal. This paper is a part of a Master thesis [6] and describes a new type of DRFM-modulator that uses digital signal processing in the frequency-domain for generation of false targets [1]. The modulator is able to produce a radar scene with a number of complex false targets constructed of many single reflectors with individual modulation and with a credible background. Some of the different strategies for the modulator topology will be introduced and discussed. The modulator is being implemented using parallel digital logic in a number of Field Programmable Gate Arrays (FPGA) on a single printed circuit board (PCB) for use in FFIs experimental radar jammer named EKKO II [4]
milstar: The new IOADCDACD1.5G mezzanine card from Annapolis Micro Systems was built specifically for use as a DRFM, and it has some impressive specs. Its two analog input and output channels have around 600 MHz instantaneous bandwidth each, which is respectable and covers a good range of applications. The board’s latency, though, is where it really shines. The latency from SMA to SMA connector is only 39 ns when going through the user FPGA space, or even lower when using a digital bypass. This makes it well suited to self-protection applications. Its board support package is also designed to make the integration of a user’s DRFM kernel simple, which should be refreshing to anyone who has had to build a DRFM out of an FPGA board that wasn’t really designed to be one” – a DRFM Industry Expert The WILDSTAR G2 Dual 1.5 GSps 12-Bit ADC & DAC Mezzanine Card is shipped with a custom heatsink which enables proper cooling of the ADC. An on-board temperature monitor is also supplied which allows for real-time monitoring of the ADC’s internal die temperature. The WILDSTAR G2 Dual 1.5 GSps 12-Bit ADC & DAC Mezzanine Card provides high fidelity and high speed analog-to-digital conversion along with a rugged design. https://www.annapmicro.com/products/wildstar-dual-1-5-gsps-12-bit-adcdac-converter-mezzanine-card/
milstar: Posted on June 5, 2014 by aluongo Annapolis, Maryland – June 5, 2014 – Annapolis Micro Systems, Inc. announced today that they have been recognized by Lockheed Martin Corporation as one of their Outstanding Suppliers. Though Lockheed Martin has thousands of suppliers, only a few small businesses are recognized for doing an outstanding job of providing products and support during the last year and for their outstanding quality in goods and services. This entry was posted in Featured News, Press Releases. Bookmark the permalink. Post navigation
milstar: https://prezi.com/tesgt-dwnlkj/digital-radio-frequency-memory-drfm/ DRFM sozdaet dlja radara loznuju cel
milstar: file:///C:/Users/Mubariz/Downloads/Advanced-SIGINT-Capability-for-a-SWaP-constrained-Platform-case-study.pdf
milstar: Common SIGINT System 4000 http://www.northropgrumman.com/Capabilities/AirborneSIGINTProductLine/Documents/CSS-4000_datasht.pdf
milstar: http://www.e2v-us.com/shared/content/resources/File/documents/broadband-data-converters/doc0869B.pdf
milstar: EV12AS200VZPY http://www.e2v.com/content/uploads/2014/09/EV12AS200xZPY-Qualification-Report.pdf -40 +110 grad C Die size 4.82 mm * 4.82 mm Wafer lab - Infineon FpBGA 196 15*15*1.2 mm 200 Ghz SiGE Bipolar Pitch -1 mm
milstar: EV12AS200ZPY http://www.e2v.com/resources/account/download-datasheet/1784 Gain flatness 1300 -1800 mhz 1.33 gaps -0.9db SINAD 1490 mhz 1.5 gsps 55/52 dBFS ENOB -8.8/8.4 bit SFDR 67/55 dBFs
milstar: EV12AS200ZPY http://www.e2v.com/resources/account/download-datasheet/1784 Gain flatness 1300 -1800 mhz 1.33 gaps -0.9db SINAD 1490 mhz 1.5 gsps 55/52 dBFS ENOB -8.8/8.4 bit SFDR 67/55 dBFs
milstar: http://www.apissys.com/views/media_produit/datasheets/11/AF202-0.pdf 2 *1.5 gsps 12 bit Abc -50 gramm Fin 1.5 ghz, snd -55 dBFs ,SFDR -67dbc,ENOB -8.7 bit 2*15 gsps
milstar: Why Oversample when Undersampling can do the Job? System designers most often tend to use ADC sampling frequency as twice the input signal frequency. As an example, for a signal with 70-MHz input signal frequency with 20-MHz signal bandwidth, system designers often use more than 140 MSPS sampling rate for ADC even though anything above 40 MSPS is sufficient as the sampling rate. http://www.ti.com/lit/an/slaa594a/slaa594a.pdf Nyquist-Shannon Sampling theorem, which is the modified version of the Nyquist sampling theorem, says that the sampling frequency needs to be twice the signal bandwidth and not twice the maximum frequency component, in order to be able to reconstruct the original signal perfectly from the sampled version. If B is the signal bandwidth, then Fs > 2B is required where Fs is sampling frequency. The signal bandwidth can be from DC to B or from f1 to f2 where B = f2 – f1. The aliasing effect due to the undersampling technique can be used for our advantage. When a signal is sampled at a rate less than twice its maximum frequency, the aliased signal appears at Fs – Fin, where Fs is the sampling frequency and Fin in the input signal frequency. In the above case, if we sample the 70-MHz signal with 100 MSPS sampling rate, the aliased component will appear at 30 MHz (100 – 70). As we know in advance that the signal is aliased, we can recover the actual frequency by using the Fs – Fin relationship. The undersampling technique allows the ADC to behave like a mixer or a down converter in the receive chain. For a band-limited signal of 70 MHz with a 20-MHz signal bandwidth, if the sampling rate (Fs) is 100 MSPS, the aliased component will appear between 20 MHz to 40 MHz (30 ±10 MHz). We will use the example of a 70-MHz signal with 20-MHz bandwidth (60 MHz to 80 MHz) for the discussion throughout this paper. For a radar application and for communication systems, generally 70 MHz is used as IF (intermediate frequency) with a specific bandwidth ranging from a few KHz to a few MHz. The maximum frequency component is 80 MHz in this signal. For an oversampling case, the minimum sampling rate is more than 160 MSPS. To keep this band of 60 MHz to 80 MHz in the middle of the first Nyquist Zone, the sampling frequency is 280 MSPS. This signal in frequency domain is shown in Figure 1.
milstar: Are there any Advantages of Oversampling? Yes. There are some specific advantages of oversampling which are described below. 3.1 Processing Gain When the signal is oversampled a greater number of times than its signal bandwidth, then the processing gain is achieved in addition to the SNR shown in the ADC datasheets. For example, for the ADS4149, at 70 MHz, the SNR will be around 72 dB at the sampling rate of 200 MSPS. For our example of 70 MHz with 20-MHz bandwidth, the signal is oversampled by 10 times with respect to signal bandwidth. Note that with respect to the signal frequency of 70 MHz, it is oversampled only around 3 times. Due to oversampling of 10 times to the bandwidth, system designers get the extra advantage of processing gain in addition to the actual SNR mentioned in the datasheet. For Fs of 200 MSPS, the SNR of 72 dB is for a Nyquist bandwidth of Fs/2, that is, 100 MHz. For the measurement of SNR of the ADC, the noise in the entire band of 100 MHz is considered in this case. The processing gain is achieved by using the following formula: Process Gain = 10 log ((Fs/2)/BW) Where Fs is the sampling Rate; BW is the signal bandwidth; For the oversampling example, BW is 20 MHz, Fs is 200 MHz. If we use the above formula, the processing gain is around 7dB. The total SNR can be calculated using the following formula: SNRtotal = SNRds + Process Gain Where SNRtotal is the total SNR after adding the processing gain and SNRds is the SNR value provided in the datasheet (without the processing gain). SNRtotal is 79 dBFS (72 + 7) using the above formula.
milstar: ADS54J60 Dual-Channel, 16-Bit, 1.0-GSPS Analog-to-Digital Converter http://www.ti.com/lit/ds/symlink/ads54j60.pdf SNR Fin 170 mhz -70dBFS 69.8 dBFS, SFDR -88 dbc Fin 350 mhz -67.5 dBFS Input 1.9 pp ---------------- Dlja Fin 170 mhz BW= 20 mhz Process Gain = 10 log ((Fs/2)/BW) 10 log (500/20)=25 = +14 db 69.8 +14 db = 83.8 dBFS SINAD dlja BW =40 mhz 80.8 dBFS The ADS54J60 has a thermal noise of approximately 71.1 dBFS and an internal aperture jitter of 145 fs. The SNR, depending on the amount of external jitter for different input frequencies, is shown in Figure 124.
milstar: For example, consider radar using a 30-MHz bandwidth waveform at an IF of 800 MHz. If this is sampled using an A/D converter at a sample rate of 2.0 GSPS to a resolution of 12 bits, the output bandwidth of the data would be 1000 MHz, far in excess of the signal bandwidth, and the output data rate from the converter would be 3.0 GBytes/s. http://www.edn.com/design/analog/4431036/3/Demand-for-digital--Challenges-and-solutions-for-high-speed-ADCs-and-RADAR-systems If the data is decimated by a factor of 16 using a DDC, not only does the decimation provide some increased noise reduction but the output data rate is reduced to below 625 MBytes/s, which enables data transportation using only a single JESD204B lane! This significantly reduces the overall system power required. With the ability to dynamically configure the DDCs or bypass them as needed, new high-speed ADCs provide the option of switching between different modes to support power and implement optimized solutions as needed and enable the feature sets needed for cognitive radar applications. New GSPS ADCs provide solutions to not only overcome existing challenges but to further optimize the system. In supporting digitization closer to the antenna these converters provide unparalleled linearity as well as an analog bandwidth of over 3 GHz, enabling under-sampling of the L and most of the S frequency bands. This enables direct RF sampling within these frequency bands, reducing component count and system size by eliminating mixer stages. For higher frequency systems this also enables higher IFs to be used, providing options for reducing the number of mixing stages and filters, as well as increasing the frequency planning options as a wide range of IFs can be used. ------------- The latest GSPS ADCs are able to provide in excess of 75 dBc SFDR, which is nearly a 20 dBc improvement over devices that have been available in the last decade. This significant leap is even more critical when competing with recent communications infrastructure frequency allocation To explore this further, Figure 1 illustrates a high level overview of a typical current X-band radar system. Within this system two analog mixing stages are typically utilized. The first stage mixes the pulsed radar return to a frequency of around 1 GHz and the second to an IF in the region of 100 to 200 MHz to enable sampling of the signal using a 200 MSPS or lower A/D converter, to a resolution of 12 bits or higher. --------------------- Using a GSPS converter with an analog bandwidth in excess of 1.5 GHz already supports digitization of the first IF, but in many cases the performance of current GSPS ADCs has limited the acceptability of this solution as the linearity and noise spectral density of the device has not met the system requirements ---------------
milstar: As with modern test equipment, such as spectrum analyzers—many of which rely on high-speed ADCs and digital processing following an input signal path with frequency downconversion to an IF section—modern radar systems are as much defined by their digital circuitry as by their analog RF/microwave circuitry. The bandwidth and sampling rates of the ADCs set the limits for the radar’s IF stage, while the resolution of the ADCs (in bits) determines the resolution of the radar system receiver. Similarly, the DACs help generate complex modulated pulsed signals for a radar transmitter, relying on frequency upconversion and trusted RF/microwave components (such as amplifiers and filters) for the signal path to the radar system’s transmit antennas. http://defenseelectronicsmag.com/systems-amp-subsystems/radar-systems-now-rely-data-converters
milstar: The ADC used is ADC12b1800RF from Texas Instruments. It is based on calibrated folding and interpolating architecture and has an input bandwidth of 2.7 GHz in non-DES mode and 1.2 GHz in DESI and DESQ mode, maximum sampling rate of 3.6 GSPS in interleaved mode and 1800 MSPS in dual ADC mode, 12 bit of output. ENOB of 8.7 bits, SNR of 54.3 dB, SFDR of 64 dBC for I/P = 1448 MHz @ -0.5 dBFS. Linear Frequency Modulated (LFM) waveform with 10us pulse width and center frequency of 1.3 GHz http://www.radarindia.com/irsi13papers/13-FP-122.pdf
milstar: Noise Considerations in High Speed Converter Signal Chains http://www.analog.com/media/en/training-seminars/tutorials/MT-230.pdf
milstar: http://www.gdsatcom.com/Electronics/Data%20Sheets/14368_C.pdf X-Band Low Noise Amplifiers LXA-7500 Series
milstar: http://www.digikey.com/web%20export/supplier%20content/TI_296/mkt/imaging/radar.pdf?redirected=1
milstar: Overview of Radar DMTI Processing The SPS-48E radar (Fig. 1) uses a triple conversion receiver. ########### The system is wideband until the second intermediate frequency (IF) conversion, where the individual beams are bandpass filtered and separated. Since three beams are used in the DMTI, there are three coherent oscillator frequencies (one for each beam) in the final conversion of the receiver (final IF is about 1.5 MHz). ################ A single analog-to-digital (A/D) converter is used for each beam. In-phase and quadrature (I/Q) data are developed based on samples that are spaced at multiples of 90° at the IF frequency. The interpolation filter develops the I/Q estimates from A/D samples (see the boxed insert, Intermediate-Frequency Sampling Technique). The I/Q data preserve the amplitude and phase of the IF radar return. The amplitude of the radar return is computed as ( ). I Q 2 2 + The phase of the return is computed as tan21 (Q/I). From pulse to pulse, a phase progression will be seen on moving targets due to Doppler, and no phase progression will be seen on stationary reflectors. It is this phase progression on moving targets that allows such targets to be separated from stationary reflectors (clutter). To remove clutter and pass targets, DMTI filters are employed in each beam independently. A bank of digital filters is used to cover the region between low velocity (small phase shift per pulse) and higher velocity (near 360° phase shift per pulse). Targets moving at speeds such that they present more than a 360° phase progression per pulse are said to be velocity ambiguous, since the radar pulse repetition interval causes aliasing. For example, a phase progression of 400° per pulse appears exactly as a phase progression of 40° per pulse. To avoid velocity blinds (i.e., targets moving at speeds such that their phase progression is 360° per pulse, thus appearing as 0° per pulse), the pulse repetition frequency is jittered on a burst-to-burst basis. This ensures that the phase progression presented by the target will vary on a burst-to-burst basis, and thus the target will not be velocity blinded on all bursts http://www.jhuapl.edu/techdigest/TD/td1803/roul.pdf Description The AN/SPS-48G is a long-range, three-dimensional (3D) Air Search Radar that will be installed on CVN, LHA, LHD, and LPD 17 class ships. The AN/SPS-48G is used to find full volumetric detection data for Ships Self Defense System and the Cooperative Engagement Capability (CEC), Air Intercept Control, Anti-Ship Cruise Missile detection including Low Elevation and High Diver targets, backup aircraft marshalling, and the new Hazardous Weather Detection and Display Capability. http://www.navy.mil/navydata/fact_display.asp?cid=2100&tid=1250&ct=2 AN/SPS-48E - Compared to the C variant, the SPS-48E has twice the radiated power, increased receiver sensitivity, four stage solid-state transmitter, half the components of a -48C and built-in testing for easier diagnostics. Originally developed as part of the New Threat Upgrade (NTU) Program to support the SM-2 Launch On Search (LOS) capability. 1975 under the Guided Missile Frigate Anti-Air Warfare Modernization Program. The AN/SPS-48E included a digital receiver and signal processor that could automatically detect and track very small targets, even when jammed. It was included in the New Threat Upgrade of the 1980s. The deployment of the AN/SPY-1 and the end of the Cold War led to the decommissioning of a large number of such ships, and many of these vessels AN/SPS-48 sets were reused on aircraft carriers and amphibious ships, where it is used to direct targets for air defense systems such as the Sea Sparrow and RIM-116 SAM missiles. Existing sets are being modernized under the ROAR program to AN/SPS-48G standard for better reliability and usability. ################# INTERMEDIATE-FREQUENCY SAMPLING TECHNIQUE To develop in-phase (I) and quadrature (Q) data, the SPS-48E radar uses an intermediate-frequency (IF) sampling technique with an IF bandwidth of approximately 400 kHz, IF center frequency of about 1.5 MHz, and analog-to-digital (A/D) sampling frequency of 6 MHz. There is a precise 4:1 relation between the IF sample frequency and the IF center frequency. If modulation effects across the received pulsewidth are ignored, the echo may be thought of as several cycles of a sine wave. The sine wave is sampled at four times its rate, i.e., every 90°. Therefore, alternate samples will be in quadrature with each other. To account for modulation effects across the pulse, one sample is defined to be “I”; two leading and two trailing samples are combined by the following equation to create the “Q” sample (s): 180° phase shift 90° phase shift Time Q ssss =− − + + 1 16 9 16 9 16 1 16 1234 Q I QI Q I Q s s Is s −− −− 1234 This technique provides accuracy acceptable for the clutter cancellation requirements of the SPS-48E lowelevation-mode DMTI. If higher clutter cancellation is required, a more elaborate finite impulse response filter for both the I and the Q channel is required. The advantage of the current technique is that I/Q data are developed with only a single A/D converter. The two baseband analog channels in a conventional receiver are not required, and aliasing due to channel gain mismatch is avoided. Amplitude modulation effects across the received pulse do, however, cause some degradation.
milstar: Overview of Radar DMTI Processing The SPS-48E radar (Fig. 1) uses a triple conversion receiver. ########### The system is wideband until the second intermediate frequency (IF) conversion, where the individual beams are bandpass filtered and separated. Since three beams are used in the DMTI, there are three coherent oscillator frequencies (one for each beam) in the final conversion of the receiver (final IF is about 1.5 MHz). ################ A single analog-to-digital (A/D) converter is used for each beam. In-phase and quadrature (I/Q) data are developed based on samples that are spaced at multiples of 90° at the IF frequency. The interpolation filter develops the I/Q estimates from A/D samples (see the boxed insert, Intermediate-Frequency Sampling Technique). The I/Q data preserve the amplitude and phase of the IF radar return. The amplitude of the radar return is computed as ( ). I Q 2 2 + The phase of the return is computed as tan21 (Q/I). From pulse to pulse, a phase progression will be seen on moving targets due to Doppler, and no phase progression will be seen on stationary reflectors. It is this phase progression on moving targets that allows such targets to be separated from stationary reflectors (clutter). To remove clutter and pass targets, DMTI filters are employed in each beam independently. A bank of digital filters is used to cover the region between low velocity (small phase shift per pulse) and higher velocity (near 360° phase shift per pulse). Targets moving at speeds such that they present more than a 360° phase progression per pulse are said to be velocity ambiguous, since the radar pulse repetition interval causes aliasing. For example, a phase progression of 400° per pulse appears exactly as a phase progression of 40° per pulse. To avoid velocity blinds (i.e., targets moving at speeds such that their phase progression is 360° per pulse, thus appearing as 0° per pulse), the pulse repetition frequency is jittered on a burst-to-burst basis. This ensures that the phase progression presented by the target will vary on a burst-to-burst basis, and thus the target will not be velocity blinded on all bursts http://www.jhuapl.edu/techdigest/TD/td1803/roul.pdf Description The AN/SPS-48G is a long-range, three-dimensional (3D) Air Search Radar that will be installed on CVN, LHA, LHD, and LPD 17 class ships. The AN/SPS-48G is used to find full volumetric detection data for Ships Self Defense System and the Cooperative Engagement Capability (CEC), Air Intercept Control, Anti-Ship Cruise Missile detection including Low Elevation and High Diver targets, backup aircraft marshalling, and the new Hazardous Weather Detection and Display Capability. http://www.navy.mil/navydata/fact_display.asp?cid=2100&tid=1250&ct=2 AN/SPS-48E - Compared to the C variant, the SPS-48E has twice the radiated power, increased receiver sensitivity, four stage solid-state transmitter, half the components of a -48C and built-in testing for easier diagnostics. Originally developed as part of the New Threat Upgrade (NTU) Program to support the SM-2 Launch On Search (LOS) capability. 1975 under the Guided Missile Frigate Anti-Air Warfare Modernization Program. The AN/SPS-48E included a digital receiver and signal processor that could automatically detect and track very small targets, even when jammed. It was included in the New Threat Upgrade of the 1980s. The deployment of the AN/SPY-1 and the end of the Cold War led to the decommissioning of a large number of such ships, and many of these vessels AN/SPS-48 sets were reused on aircraft carriers and amphibious ships, where it is used to direct targets for air defense systems such as the Sea Sparrow and RIM-116 SAM missiles. Existing sets are being modernized under the ROAR program to AN/SPS-48G standard for better reliability and usability. ################# INTERMEDIATE-FREQUENCY SAMPLING TECHNIQUE To develop in-phase (I) and quadrature (Q) data, the SPS-48E radar uses an intermediate-frequency (IF) sampling technique with an IF bandwidth of approximately 400 kHz, IF center frequency of about 1.5 MHz, and analog-to-digital (A/D) sampling frequency of 6 MHz. There is a precise 4:1 relation between the IF sample frequency and the IF center frequency. If modulation effects across the received pulsewidth are ignored, the echo may be thought of as several cycles of a sine wave. The sine wave is sampled at four times its rate, i.e., every 90°. Therefore, alternate samples will be in quadrature with each other. To account for modulation effects across the pulse, one sample is defined to be “I”; two leading and two trailing samples are combined by the following equation to create the “Q” sample (s): 180° phase shift 90° phase shift Time Q ssss =− − + + 1 16 9 16 9 16 1 16 1234 Q I QI Q I Q s s Is s −− −− 1234 This technique provides accuracy acceptable for the clutter cancellation requirements of the SPS-48E lowelevation-mode DMTI. If higher clutter cancellation is required, a more elaborate finite impulse response filter for both the I and the Q channel is required. The advantage of the current technique is that I/Q data are developed with only a single A/D converter. The two baseband analog channels in a conventional receiver are not required, and aliasing due to channel gain mismatch is avoided. Amplitude modulation effects across the received pulse do, however, cause some degradation.
milstar: Динамический диапазон радара AN/FPQ программы Аполлон более 120 дб Антенна 8.8 метра диаметром C band 5.4-5.9 Ghz 4.8 квт средней мощности,3 мегаватта импульсной мощности промежуточная частота-30 мегагерц, полоса сигнала -1.6 мегагерц Дальность более 60 000 километров при разрешении +- 2 метра http://en.wikipedia.org/wiki/AN/FPQ-6 http://ntrs.nasa.gov/archive/nasa/casi.ntrs.nasa.gov/19680003409_1968003409.pdf
milstar: The three radar intermediate-frequency inputs to the A/D board are 20 MHz bandwidth centered at 10 MHz, and are thus sampled with a 40 MHz clock http://www.ll.mit.edu/publications/journal/pdf/vol21_no1/21_1_7_Eshbaugh.pdf FIGURE 16. Single-channel radar channel processing performed by DPCS for a typical stretch waveform.
milstar: an/tpy-2 We assume a module duty factor of 0.2, which is consistent with the module peak and average powers discussed above.[8] With the 1 millisecond pulses length assumed above, this gives fP = 200 Hz. Thus for our baseline case which integrates 20 pulses, the dwell time will be 100 milliseconds. http://mostlymissiledefense.com/2012/09/21/ballistic-missile-defense-radar-range-calculations-for-the-antpy-2-x-band-and-nas-proposed-gbx-radars-september-21-2012/ S/N: For our baseline case, we consider two values of S/N. First a low value of S/N = 20 (which we refer to as the “detection” value) and a higher figure of S/N = 100 (which we refer to as the “discrimination” value).[9] LS: We estimate LS = 8 dB = 6.3.[10] Then for our TPY-2 baseline cases we get: R = 870 km detection (S/N = 20) R = 580 km discrimination (S/N = 100)
milstar: In the linear ASIC design arena there is an even wider range of services — where full turnkey delivery is offered. Internally developed linear designs are sent out for fabrication and packaging, but returned for advanced on-site testing. Raytheon currently tests and delivers over 100K linear ICs per year. http://www.cs.wustl.edu/~schmidt/Tech_030612.pdf
milstar: The SPS-48E radar (Fig. 1) uses a triple conversion receiver. The system is wideband until the second intermediate frequency (IF) conversion, where the individual beams are bandpass filtered and separated. Since three beams are used in the DMTI, there are three coherent oscillator frequencies (one for each beam) in the final conversion of the receiver (final IF is about 1.5 MHz). A single analog-to-digital (A/D) converter is used for each beam. In-phase and quadrature (I/Q) data are developed based on samples that are spaced at multiples of 90° at the IF frequency. The interpolation filter develops the I/Q estimates from A/D samples http://techdigest.jhuapl.edu/TD/td1803/roul.pdf The clutter-to-noise ratio presented to the radar by this land has peaks on the order of 100 dB, thus Figure 7. Beam 1 land clutter data collected approximately 14 nmi off the coast of Point Loma, California, using the normal 3-1-2 beam transmit sequence with a wideband limiter at 36 dB: (a) normal sensitivity time control, (b) constant 30-dB attenuation, (c) constant 50- dB attenuation, (d) constant 70-dB attenuation. Noise level is approximately 24 dB. Clutter-to-noise ratios on the order of 100 dB are seen. 20 10 20 10 Range (nmi) Range (nmi) 20 10 20 10 Range (nmi) Range (nmi) 55 80 60 65 70 75 Bearing (deg) 55 80 60 65 70 75 Bearing (deg) 55 80 60 65 70 75 Bearing (deg) 55 80 60 65 70 75 Bearing (deg) > 60 60 ≥ 52 52 ≥ 44 44 ≥ 36 36 ≥ 28 28 ≥ 20 ≤ 20 Amplitude (dB) (a) (b) (c) (d) confirming that land clutter can definitely present very large clutter echoes, an enormous challenge for radar systems.
milstar: USS Abraham Lincoln receives AN/SPS-48 primary air search radar antenna 0 15 May 2015 Newport News Shipbuilding, along with the US Navy, has successfully reinstalled the AN/SPS-48 primary air search radar antenna on the aircraft carrier, USS Abraham Lincoln (CVN 72). This new development is part of the ongoing refuelling and complex overhaul (RCOH). Combat Systems Department division officer lieutenant Loudon Westgard said: "Installing the radar on time is one of the most important measures taken in the refuelling and complex overhaul process. "This was a major accomplishment, and the shipyard workers and sailors aboard Lincoln should be very proud of the progress they are making." The long-range, three-dimensional air search radar AN/SPS-48 a for 360° coverage. It is also capable of dectecting the height of a target above the surface of the water. http://www.naval-technology.com/news/newsuss-abraham-lincoln-receives-ansps-48-primary-air-search-radar-antenna-4578470
milstar: В группу компаний «Ангстрем» входит расположенный в Зеленограде АО «Ангстрем-Т» – научно-производственный комплекс по производству субмикронных полупроводниковых изделий по технологическим нормам 130–90 нм, с перспективой перехода на производственный уровень 65 нм и нижe http://oborona.gov.ru/news/view/12040 для высокоскоростных аналого-цифровых преобразователей 1-5 gigasample достаточно
milstar: http://www.e2v.com/resources/account/download-datasheet/4368
milstar: BarsMonster 21 февраля 2014 в 00:10 Микрон: Чуть детальнее о производстве 65нм микросхем в России IT-инфраструктура Вчера все отечественные сайты облетела новость о том, что в России Микроном разработана технология производства микросхем по нормам 65нм (или даже «В России выпущены первые 65-нм микросхемы»). Ранее Микрон имел лицензированную у STMicroelectronics технологию 90нм. Попробуем чуть детальнее разобраться, как там обстоят дела. Микрон на этот раз на удивление опубликовал достаточно много информации. На фотографиях — разметка одного тестового транзистора и фотографии сделанные электронным микроскопом. Под катом — посмотрим, как это можно было сделать и сравним с Intel 65nm. Сравнение техпроцессов Микрон опубликовал таблицу с параметрами их техпроцесса. Для сравнения, я добавил техпроцесс Intel 65нм: Технология Микрон 65нм Микрон 90нм Intel 65нм Gate length 45нм На фотографии 54нм 65нм 35-38нм +SiGe stress Gate oxide thickness (electrical) 2.2nm (n) / 2.2nm (p) 2.2nm (n) / 2.2nm (p) 1.2nm SiON Interconnect 9-Cu + 1-Al 7-Cu + 1-Al 8-Cu Metal 1 pitch 0.18µm 0.24µm 0.21µm Inter-level dielectric k = 2.9 k = 2.9 k=2.9 M1 pitch (шаг первого уровня металлизации) вызывает некоторое сомнение — по мере уменьшении шага металла M1 менее 0.2-0.3мкм (для 65нм технологии) быстро падает скорость работы микросхемы из-за увеличения RC-константы, потому Intel и не стал его уменьшать менее 0.21-0.22мкм. Очередное напоминание, что именно межсоединения являются основным тормозом прогресса микроэлектроники. Длина затвора и толщина подзатворного диэлектрика говорит о том, что это LP техпроцесс — с низким потреблением и меньшей скоростью работы. Так что сделать процессор, аналогичный первым Core2Duo на Микроне пока не выйдет, но и для LP техпроцессов есть масса применений. Количество металлов позволяет реализовывать процессоры любой сложности. В погоне за 65нм Как мы помним, разрешение оптической фотолитографии подчиняется критерию Рэлея: На данный момент самая продвинутая установка фотолитографии на Микроне (сканер ASML PAS/1150C) имеет NA=0.75 и работает на длине волны 193нм. Параметр k — множитель используемых «ухищрений», позволяющих улучшить получаемое разрешение. k для фотолитографии без хитростей — 0.4. В случае Микроновских 90нм — k был уже 0.35. Чтобы с тем же сканером получить честные 65нм, k нужно было бы как-то снизить до 0.25 (т.е. добавить достаточно много хитростей). Однако учитывая слова из пресс-релиза («были разработаны специальные алгоритмы внесения оптической коррекции фотолитографии»), обычной, классической топологии тестового транзистора (не используя «одномерные» структуры) и длину затвора на фотографии (54нм) — на данный момент похоже просто на текущем оборудовании без дополнительных хитростей сделали транзисторы с затвором меньшего размера для первых тестов (это резко увеличивает процент брака, но для тестовых транзисторов приемлемо) + отработали новые технологические шаги техпроцесса, отличающиеся от 90нм. Говорят, в Марте 2014 года на Микроне ждут приход нового сканера — и там 65нм получится без дополнительных хитростей, а с хитростями — и более тонкие техпроцессы (45нм, ниже?). Вот тогда, к концу года (а то и в 2015) — и выйдут первые полноценные микросхемы по технологии 65нм. Объем производства ожидается порядка 500 200мм пластин в месяц — это практически гарантирует, что производство получится очень дорогим, и доступным только для государства. Наконец о возможных хитростях 65нм можно было получить и на текущем оборудовании Микрона. Достаточно вспомнить про то, как Интел в 2007-м сделал 45нм техпроцесс на «сухой» фотолитографии используя сканер с апертурой 0.93 (у Микрона напомню 0.75): критические слои экспонировали в 2 захода: в первый заход экспонировали ряд горизонтальных линий (используя dipole illumination, поляризацию — так можно достичь большего разрешения, но только вдоль одной оси). Затем второй экспозицией нарезали линии на кусочки нужной формы. Результат на фотографии. Собственно, аналогичным образом получается разрешение 32нм. Этот подход позволяет получить k=0.21, и для Микроновского сканера это позволило бы получить 55нм техпроцесс. Но безусловно объем работ был бы весьма внушительным. Резюме Говорить о «65нм микросхемах сделанных в России» пока преждевременно — это единичные тестовые транзисторы на существующем оборудовании. Технология LP (бОльшая длина затвора, более толстый подзатворный диэлектрик) — с низким потреблением и меньшей скоростью, ожидать процессоров аналогичных Intel 65nm (первые Core2Duo) не стоит. С новым оборудованием (в первую очередь сканер), которое должно заработать на Микроне в этом году — будут возможна как 65нм технология, так и более тонкие. Из-за очень маленького объема производства (500 пластин в месяц) себестоимость пластины обещает быть довольно высокой, завалить конкурентоспособной гражданской 65нм продукцией рынок не выйдет. Но этого и не требовалось.
milstar: БЦВМ на процессорном модуле с Эльбрус 4С Производительность БЦВМ (при работе с 32 разрядными числами), ГФлопс Не менее 35 Программное обеспечение операционную систему «Эльбрус», драйвера носителя мезонинов Габариты (Д x Г x В), мм не должны превышать размеров 280×230×110 Масса, кг Не более 5,5 Средняя наработка на отказ в полете, ч не менее 9000 http://www.ipmce.ru/custom/path7/path1/path2/
milstar: STRECHING THE DYNAMIC RANGE OF ADCS WHITE PAPER http://www.rfel.com/upload/docs/12013StrechingthedynamicrangeofADCsWP1.0.pdf
milstar: http://www.ti.com/lit/ds/symlink/adc12dj3200.pdf enob 9 bit 997 mhz sfdr -69 dBFS 997 mhz up to 6.4 GSPS in single channel mode Up to 3.2 GSPS in dual channel mode Analog input bandwidth (-3 dB): 8.0 GHz allows direct RF sampling of L-band,S-band, C-band and X-band for frequency agile systems. Power consumption: 3.0 W ################## Time interleaving is achieved internally through 4 active cores. ######### In dual channel mode, two cores are interleaved per channel to increase the sample rate to 2x the core sample rate. In single channel mode, all 4 cores are time interleaved to increase the sample rate to 4x
milstar: http://www.mwrf.com/systems/differences-between-receiver-types-part-1 ##### As a general statement, a properly designed superheterodyne receiver will have far superior sensitivity and immunity to interference when compared to a direct conversion receiver. ############################### For a phased array digital beam-forming the challenge becomes size, power, and cost constraints when many receivers are needed across the array. http://www.mwrf.com/components/receiver-design-considerations-digital-beamforming-phased-arrays Peter Delos is lead RF/RFIC engineer for Lockheed Martin Corp.
milstar: AD9208 0.028 micron CMOS 2*14 bit 196 ball bga 12*12 mm http://www.analog.com/media/en/technical-documentation/data-sheets/AD9208.pdf ENOB 9.6 1800 mhz a in -9dbfs SINAD 59.7 dbfs SFDR -81 dbfs ########### eight-lane operation, with lane rates of up to 16 Gbps/lane. Using default settings, total power per channel at 3 Gbps is 1.65 W. temperature range of -40°C to +85°C, the AD9208 costs $1326. Based on a 28 nm CMOS process, the AD9208 dual 14 bit ADC from Analog Devices enables IF sampling of signals at up to 9 GHz (-3 dB point) When wide signal bandwidths are required, gigasampling high speed data converters from ADI provide the direct RF conversion capabilities to support advanced multiband radios designs. Frequency agility and signal aggregation are necessary for ease of deployment in regions where service providers own fragmented frequency bands and desire a single radio design to cover them all. RF DACs and RF ADCs from ADI support wide signal bandwidths up to 1.5 GHz. Enhanced JESD204B serial lanes support rates up to 15 Gbps, reducing the number of lanes required for data transport. Outstanding linearity performance enables direct signal generation up to 4.2 GHz and direct signal capture up to 6 GHz http://www.analog.com/media/en/news-marketing-collateral/product-highlight/AD9208-AD9172-High-Speed-Converters.pdf
milstar: 4. Studio-quality audio Data converters are also playing a critical role in enabling the high-resolution audio content for ultra-high-quality music playback. They help filter the unwanted noise and provide immunity against high jitter. Secondly, they ensure low power consumption to maximize the battery life of music playback devices like headphones. The CS43130 digital-to-analog converter from Cirrus Logic is a case in point. It consumes 23 milliwatts of power, which, according to the audio chipmaker, is four times less than other high-fidelity DACs available in the market. And it offers up to 32-bit resolution and 384-kHz sampling rate to deliver superior audio quality.
milstar: Benefits of Using 28 nm and Lower Process Converters As converter transistor sizes decrease, the parasitic gate capacitance is reduced, and converters are able to be operated at faster sample rates. These faster rates result in generally wider Nyquist bandwidths, enabling the broad instantaneous bandwidths required for EW systems. Additionally, smaller transistor size results in the ability to fit more transistors onto a given die, resulting in greater converter channel counts per package. Faster sample rates and greater channel counts provide the ability to achieve both the broad instantaneous spectrum sniffing and simultaneous multi-band interrogation required for signals intelligence (SIGINT) systems. Reduced feature sizes could potentially enable the integration of both a DAC and ADC core into a single monolithic package, creating the ability to design full-duplex EW transmitter and receiver systems with a single converter chip. Further, smaller transistor sizes allow for additional circuitry to be added to converter packages, such as numerically-controlled oscillators (NCO) and digital down-converters (DDC), to simplify the large digital signal processing (DSP) tasks required by EW systems. 28 nm processes lead to smaller cross-sections, usually resulting in fewer radiation-induced soft errors compared to similar features in a 65 nm process. The reduced damage from stray ionizing energy creates more robust electronic protect (EP) or electronic support (ES) systems. http://www.microwavejournal.com/articles/29758-its-time-to-convert-our-ew-radio-designs
milstar: российский скоростной ацп конвейерного типа Resolution 14 Bit Sample rate 125 MSPS; Parallel CMOS and LVDS output; Single power supply 1.8V; SNR - 69.9dBFS; INL - 3.0 LSB; 180 nm CMOS process. http://www.milandr.com/ICDCS.php#/
milstar: российский скоростной ацп конвейерного типа Resolution 14 Bit Sample rate 125 MSPS; Parallel CMOS and LVDS output; Single power supply 1.8V; SNR - 69.9dBFS; INL - 3.0 LSB; 180 nm CMOS process. http://www.milandr.com/ICDCS.php#/ https://www.milandr.ru/upload/smi/konveyernyy_atsp.pdf В статье представлен первый конвейерный аналого-цифровой преобра- зователь (АЦП) 5101н В025 в разрабатываемой линейке АЦП компании «миландр». Первый быстродействующий 14 - разряд - ный АЦП в линейке преобразователей ком - пании «Миландр» К5101НВ025, выполнен- ный по технологии 0,18 мкм, достигает со- отношения сигнал/шум 64 дБ и диапазона, свободного от гармоник, 75 дБ при частоте выборки 75 Мвыб./c.
milstar: Динамический диапазон радара AN/FPQ программы Аполлон более 120 дб Антенна 8.8 метра диаметром C band 5.4-5.9 Ghz 4.8 квт средней мощности,3 мегаватта импульсной мощности промежуточная частота-30 мегагерц, полоса сигнала -1.6 мегагерц Дальность более 60 000 километров при разрешении +- 2 метра http://en.wikipedia.org/wiki/AN/FPQ-6 http://ntrs.nasa.gov/archive/nasa/casi.ntrs.nasa.gov/19680003409_1968003409.pdf ########## 37 metr Dish Lincoln laboratory radar The three radar intermediate-frequency inputs to the A/D board are 20 MHz bandwidth centered at 10 MHz, and are thus sampled with a 40 MHz clock http://www.ll.mit.edu/publications/journal/pdf/vol21_no1/21_1_7_Eshbaugh.pdf FIGURE 16. Single-channel radar channel processing performed by DPCS for a typical stretch waveform. --- The SPS-48E radar (Fig. 1) uses a triple conversion receiver. The system is wideband until the second intermediate frequency (IF) conversion, where the individual beams are bandpass filtered and separated. Since three beams are used in the DMTI, there are three coherent oscillator frequencies (one for each beam) in the final conversion of the receiver (final IF is about 1.5 MHz). A single analog-to-digital (A/D) converter is used for each beam. In-phase and quadrature (I/Q) data are developed based on samples that are spaced at multiples of 90° at the IF frequency. The interpolation filter develops the I/Q estimates from A/D samples http://techdigest.jhuapl.edu/TD/td1803/roul.pdf The AN/SPS-48G is a long-range, three-dimensional (3D), air search radar that is progressively being installed on CVN, LHA, LHD and LPD classes of ships, replacing the AN/SPS-48E. The program of record is to backfit the existing AN/SPS-48E population with the AN/SPS-48G variant from 2011 through 2021, and to keep this system operational through the year 2050. As of the end of 2016, the AN/SPS-48G is already installed or in the process of installation aboard CVNs 68-72, CVNs 74-76, LHDs 1-3, LHD 7, LHA 7 and LPDs 26-27. The AN/SPS-48G is used to provide full volumetric detection data for the Ship Self Defense System (SSDS) via the Cooperative Engagement Capability (CEC) or the SYS-2 tracker; Air Intercept Control; Anti-Ship Cruise Missile detection including low elevation and high diver targets; backup aircraft marshalling; and the new Hazardous Weather Detection and Display Capability. http://www.navy.mil/navydata/fact_display.asp?cid=2100&tid=1250&ct=2
milstar: http://www.ti.com/lit/ds/symlink/ads5482.pdf 105 msps 16 bit ADS5482 12.9 10 mhz 12.88 enob 30 mhz from dbc SFDR 98 dbc 10 mhz ,30 mhz SINAD -79.5. 79.3 dbc -----------------------------------------
milstar: http://www.analog.com/en/products/analog-to-digital-converters/standard-adc/high-speed-ad-10msps/ad9467.html#product-documentation http://www.analog.com/media/en/technical-documentation/data-sheets/AD9467-EP.pdf https://landandmaritimeapps.dla.mil/Downloads/MilSpec/Vid/V6216611.pdf AD9467 SiGe 0.18 micron 2010 year ----------------------------------------------------------- analog input full scale 2.5 v ENOB 5 mhz -12.4 97-170 mhz 12.3 210 mhz -12.2 300 mhz -12.1 SFDR 5 mhz -97 db 97 -93 db 140 -95 db 170 -92 ,210 -92 60 fms jitter #####################
milstar: http://www.analog.com/media/en/technical-documentation/data-sheets/AD9650.pdf 80 msps 16 bit SINAD 82 82 enob 13.5 9.7 mhz ,13.2 30 mhz , SFDR 95.5 ,92
milstar: http://www.analog.com/media/en/technical-documentation/data-sheets/238718fa.pdf 18 bit 15 msps SINAD 1 mhz -94.5 db 2 mhz -92 ,3 mhz -88db SFDR 1 mhz -102 db dbfs Input level 1mhz -15 dbfs SFDR - -135 dbfs or -120 dbc
milstar: http://www.analog.com/media/en/technical-documentation/data-sheets/2107fb.pdf 210 msps 16 bit sinad 30 mhz -79.5,71 mhz -784.,141 mhz -787. dbfs pga =0 SFDR 30 mhz dither off input -25dbfs -107.4 dbfs=-82 dbc ,on-124 dbfs =-99 dbc
milstar: To develop in-phase (I) and quadrature (Q) data, the SPS-48E radar uses an intermediate-frequency (IF) sampling technique with an IF bandwidth of approximately 400 kHz, IF center frequency of about 1.5 MHz, and analog-to-digital (A/D) sampling frequency of 6 MHz. There is a precise 4:1 relation between the IF sample frequency and the IF center frequency. If modulation effects across the received pulse- width are ignored, the echo may be thought of as several cycles of a sine wave. The sine wave is sampled at four times its rate, i.e., every 90 ° . Therefore, alternate samples will be in quadrature with each other. To account for modulation effects across the pulse, one sample is defined to be “I”; two leading and two trailing samples are combined by the fol- lowing equation to create the “Q” sample (s): http://techdigest.jhuapl.edu/TD/td1803/roul.pdf The AN/SPS-48G is a long-range, three-dimensional (3D), air search radar that is progressively being installed on CVN, LHA, LHD and LPD classes of ships, replacing the AN/SPS-48E. The program of record is to backfit the existing AN/SPS-48E population with the AN/SPS-48G variant from 2011 through 2021, and to keep this system operational through the year 2050. As of the end of 2016, the AN/SPS-48G is already installed or in the process of installation aboard CVNs 68-72, CVNs 74-76, LHDs 1-3, LHD 7, LHA 7 and LPDs 26-27. The AN/SPS-48G is used to provide full volumetric detection data for the Ship Self Defense System (SSDS) via the Cooperative Engagement Capability (CEC) or the SYS-2 tracker; Air Intercept Control; Anti-Ship Cruise Missile detection including low elevation and high diver targets; backup aircraft marshalling; and the new Hazardous Weather Detection and Display Capability. http://www.navy.mil/navydata/fact_display.asp?cid=2100&tid=1250&ct=2
milstar: http://www.wirelessinnovation.org/assets/Proceedings/2012Europe/2012-europe-a-4.1.3-ulbricht-presentation.pdf Analog-to-Digital Conversion – the Bottleneck
milstar: http://www.eewebinar.co.kr/webinar/attach/07-22-15_RADAR_Webcast_Update.pdf
milstar: В числе новинок «Ангстрема» будут представлены решения для систем мобильной связи, базовых станций и систем сбора данных: 12-разрядный аналого-цифровой преобразователь 5023НВ04А5, 5023НВ04В5 и 14-разрядный аналого-цифровой преобразователь 5023НВ015, а также микросхемы АЦП на 14 двоичных разрядов типа 5023НВ035, 5023НВ035Р с частотой дискретизации 150 МГц и низкой потребляемой мощностью 150 мВт. Подробнее: http://www.cnews.ru/news/top/2016-03-14_angstrem_pokazhet_vse_svoi_razrabotki 2016
milstar: http://www.dcsoyuz.com/files/content/ADC/specifikacija_5112nv035_ver1.1.pdf
milstar: The SFDR of the ADC is a key factor that restricts how much additional analogue signal processing circuitry must be used between the devices and the antennae [2],[3],[4]. This issue is recognized as a key problem in the defence research area internationally. SFDR limits the useful range and resolution of RADAR [5] and the service area of communication systems. Some results of defense funded projects in the UK, Australia and the USA have been published [6],[7],[8],[9],[10]. https://www.researchgate.net/publication/285598493_Dynamic_range_limits_of_RF_ADCs
milstar: https://www.teledyne-e2v.com/shared/content/resources/File/documents/broadband-data-converters/EV12AQ600/EV12AQ600_PDS.pdf sampling rate of 6 GSps. This high flexibility enables digitization of IF and RF signals with up to 3 GHz of instantaneous bandwidth. With an extended input bandwidth above 6 GHz (EFPBW) the EV12AQ600 allows sampling of signals directly in the C-band (4-8 GHz) without the need to translate the signal to baseband through a down- conversion stage. The latency is 126 system clock cycles. 4 channel mode at 1.5Gsps at -1dB FS output level: - Fin = 748 MHz (NZ1): ENOB: 8.7 bit / SFDR: 71 dB FS using normal bandwidth (NFPBW) - Fin = 1480 MHz (NZ2): ENOB: 8.4 bit / SFDR: 63 dB FS (NFPBW) - Fin = 1900 MHz (NZ3): ENOB: 8.1 bit / SFDR: 64 dB FS (NFPBW)
milstar: EV12AD550 is a dual S - band capable 12bit ADC intended for space applications that is built using a true single core architecture per channel providing high spectral purity. With a 3dB input bandwidth up to 4.3GHz , it allows for direct digitization in S - ban d without frequency down - conversion. Synthetic Aperture Radar systems will also be able to operate this ADC with reduced dynamic range at frequencies beyond 5GHz without frequency down - conversion https://www.teledyne-e2v.com/shared/content/resources/File/documents/broadband-data-converters/EV12AD550/EV12AD550B_DS.pdf Ea rth observation SAR payload Telecommunication satellite payload Satellite data links Satellite altimeter Satellite TWTA compensation system Satellite to satellite laser data links
milstar: https://www.teledyne-e2v.com/shared/content/resources/File/documents/broadband-data-converters/EV12AD550/Te2v_EV12AD550A_PF_EU.pdf https://www.teledyne-e2v.com/shared/content/resources/File/documents/broadband-data-converters/EV12AD550/Boost_economics_in_agile_high_throughput_SatCom_payloads-e2v.pdf
milstar: https://www.analog.com/media/en/technical-documentation/data-sheets/AD9208.pdf The AD9208 is a dual, 14-bit, 3 GSPS analog-to-digital converter (ADC). The device has an on-chip buffer and a sample-and- hold circuit designed for low power, small size, and ease of use. This product is designed to support communications applications capable of direct sampling wide bandwidth analog signals of up to 5 GHz. The −3 dB bandwidth of the ADC input is 9 GHz.
milstar: Advanced Technologies Pave the Way for New Phased Array Radar Architectures https://www.analog.com/en/technical-articles/advanced-technologies-pave-the-way-for-new-phased-array-radar-architectures.html
milstar: Advanced Technologies Pave the Way for New Phased Array Radar Architectures https://www.analog.com/en/technical-articles/advanced-technologies-pave-the-way-for-new-phased-array-radar-architectures.html A large proliferation of digital beamforming phased array technology has emerged in recent years. The technology has been spawned by both military and commercial applications, along with the rapid advancements in RF integration at the component level. Although there is a lot of discussion of massive MIMO and automotive radar, it should not be forgotten that most of the recent radar development and beamforming R&D has been in the defense industry, and it is now being adapted for commercial applications. While phased array and beamforming moved from R&D efforts to reality in the 2000s, a new wave of defense focused arrays are now expected, enabled by industrial technology offering solutions that were previously cost prohibitive. A generic beamforming phased array signal flow is shown in Figure 2. The number of elements is chosen at the system architect level, based on aperture size, power, and antenna pattern requirements. Front-end modules are behind each antenna element. https://www.analog.com/media/en/technical-documentation/tech-articles/advanced-technologies-pave-the-way-for-new-phased-array-radar-architectures.pdf
milstar: heterodyne Proven and trusted High performance Optimum spurious High dynamic range EMI immunity ------------ SWaP Many filters =================== direct conversion Maximum ADC bandwidth Simplest wideband option ---------- mage rejection I/Q balance In-band IF harmonics LO radiation EMI immunity (IP2) DC and 1/f noise ================ https://www.analog.com/en/technical-articles/advanced-technologies-pave-the-way-for-new-phased-array-radar-architectures.html The superheterodyne approach, which has been around for a hundred years now, is well proven and provides exceptional performance. Unfortunately, it is also the most complicated. It typically requires the most power and the largest physical footprint relative to the available bandwidth, and frequency planning can be quite challenging at large fractional bandwidths. The direct sampling approach has long been sought after, the obstacles being operating the converters at speeds commensurate with direct RF sampling and achieving large input bandwidth. Today, converters are available for direct sampling in higher Nyquist bands at both L- and S-band. In addition, advances are continuing with C-band sampling soon to be practical, and X-band sampling to follow. Direct conversion architectures provide the most efficient use of the data converter bandwidth. The data converters operate in the first Nyquist, where performance is optimum and low-pass filtering is easier. The two data converters work together sampling I/Q signals, thus increasing the user bandwidth without the challenges of interleaving. The dominant challenge that has plagued the direct conversion architecture for years has been to maintain I/Q balance for acceptable levels of image rejection, LO leakage, and dc offsets. In recent years, the advanced integration of the entire direct conversion signal chain, combined with digital calibrations, has overcome these challenges, and the direct conversion architecture is well positioned to be a very practical approach in many systems. Here at Analog Devices, we are continually advancing the technology for all the signal chain options described. The future will bring increased bandwidth and lower power, while maintaining high levels of performance, and integrating complete signal chains in system on chips (SoC), or system in packages (SiP) solutions.
milstar: https://www.analog.com/media/en/analog-dialogue/volume-53/number-1/high-performance-data-converters-for-medical-imaging-systems.pdf High Performance Data Converters for Medical Imaging Systems Digital Radiography The signal-to-noise ratio ( SNR ) is another important parameter that defines the intrinsic ability of the system to faithfully represent the anatomic features of the imaged body. Digital X-ray systems use 14-bit to 18-bit ADCs with SNR levels ranging from 70 dB up to 100 dB depending on the type of the imaging system and its requirements. Computed Tomography The ADC must have high resolution of at least 24 bits to achieve better and sharper images, and a fast sampling rate to digitize detector readings that can be as short as 100 μs. The ADC sampling rate must also enable multiplexing, which would allow the use of fewer converters as well as the reduction of the size and power of the entire system. Positron Emission Tomography The photons’ energy and the detection time difference impose strict requirements on the ADC, which must have good resolution of 10 to 12 bits and fast sampling rates typically better than 40 MSPS. Low noise performance to maximize the dynamic range and low power operation to reduce heat dissipation are also important for PET imaging. Magnetic Resonance Imaging ADCs for direct digital conversion of the MR signals in the most common frequency ranges at conversion rates exceeding 100 MSPS at a 16-bit depth. The requirement for dynamic range is very demanding—it typically exceeds 100 dB. Ultrasonography One of the most important requirements imposed on the AFE is the dynamic range. Depending on the imaging mode, this requirement can demand 70 dB to 160 dB to distinguish between blood signals and background noise resulting from probe and body tissue movements. Therefore an ADC must provide high resolution, a high sampling rate, and low total harmonic distortion ( THD ) to maintain dynamic fidelity of the ultrasound signal. Low power dissipation is another important requirement dictated by the high channel density of the ultrasound front end.
milstar: 1.Diagnostic Imaging Market worth $36.43 billion by 2021 2. LTE base stations 5G approx 70 billion $ in 2023
milstar: Global RADAR market size is estimated to reach $10.4 billion by 2022, growing at a CAGR of 3.9% from 2016 to 2022.
milstar: https://www.analog.com/media/en/technical-documentation/data-sheets/ad9213.pdf
milstar: https://www.electronicdesign.com/adc/inside-look-high-speed-adc-accuracy-part-2
milstar: https://www.analog.com/media/en/technical-documentation/data-sheets/ad9652.pdf APPLICATIONS Military radar and communications Multimode digital receivers (3
milstar: https://www.analog.com/media/en/technical-documentation/data-sheets/238718fa.pdf
milstar: http://www.ti.com/lit/ds/symlink/ads54j60.pdf
milstar: http://www.ti.com/lit/ds/symlink/ads54j69.pdf
milstar: http://www.ee.fju.edu.tw/pages/032_faculty/sclin/lecture/Rada_System_Design/Chapter7.pdf
milstar: Marki Microwave | 215 Vineyard Ct. | Morgan Hill, CA 95037 | PH 408.778.4200 | info@markimicrowave. com Section 4. Summary and Conclusion The T3 is a true paradigm shift in mixer technology. Perhaps the greatest achievement of the T3 is the fact that much of the existing dogma surrounding mixers has been turned upside https://www.markimicrowave.com/home/ https://www.markimicrowave.com/assets/appnotes/t3_primer.pdf - down. Since the 1960s, mixers experts have promoted the following ideas: 1. Mixers require specific LO drive over a range of approximately 3 dB. 2. Mixers compress 5 - 7 dB below the LO drive. 3. Mixer spurious performance does not always improve with increasi ng LO. 4. Mixer IIP3 is approximately 1 to 2 dB above the optimal LO drive. 5. Sine wave LO drive is acceptable, square - wave LO drive does not improve mixer performance significantly. We agree with all of the above statements, assuming we are restricting the di scussion to double balanced mixers . For the T3 mixer, the following (new) rules apply: 1. T3 mixers can operate with any LO drive above about +13 dBm. 2. T3 mixer compression is approximately equal to the LO drive itself. 3. Increasing the LO drive always improves spurious performance in a T3. 4. Increasing the LO drive always improves the IIP3 of a T3. IIP3 is approximately 10 - 15 dB higher than the LO drive. 5. Square - wave LO drive is always better than sine wave drive for a T3. Marki Microwave continues to develop the T3 technology to reach an ever - increasing customer base. In time, it is conceivable that the majority of the legacy mixer technology available today will be superseded by the T3 and its offspring technology. For these reasons, the T3 is truly a mixer for t he 21 st century.
milstar: https://mostlymissiledefense.com/2012/04/12/cobra-dane-radar-april-12-2012/ http://www.radartutorial.eu/19.kartei/01.oth/karte003.en.html The radar system uses linear frequency modulated (LFM) (intrapulse modulation). The transmitters swept bandwidth is 200 MHz (up-chirp). It's time-bandwidth product is TB = 200,000. This allows a resolution of 0.2 MHz per nanosecond, i.e. a radar range resolution of 3 ¾ ft (= 115 cm). The first receivers intermediate frequency (IF) is 490 MHz at the output of a correlation mixer, the second IF is 60 MHz As originally built, in wide-band mode Cobra Dane used a 1 ms pulse with a 200 MHz bandwidth (obtained using linear frequency modulation pulse compression) at frequencies between 1.175 and 1.375 GHz, and was limited to angles within 22.5˚ of its boresite. In wideband operation, it has a range resolution of about 3.75 feet (1.14 m). In narrowband operation, it uses frequencies between 1.215 to 1.250 GHz (corresponding to a wavelength of about 24.3 cm). In search, it uses 1 MHz pulses with lengths of 1.5 or 2.0 ms, and in track it uses six different 5 MHZ bandwidth pulses with lengths between 0.15 and 1.5 ms. The radar also has two 1.0 ms, 25 MHz bandwidth pulses used for ionospheric compensation.As originally built, in wide-band mode Cobra Dane used a 1 ms pulse with a 200 MHz bandwidth (obtained using linear frequency modulation pulse compression) at frequencies between 1.175 and 1.375 GHz, and was limited to angles within 22.5˚ of its boresite. In wideband operation, it has a range resolution of about 3.75 feet (1.14 m). In narrowband operation, it uses frequencies between 1.215 to 1.250 GHz (corresponding to a wavelength of about 24.3 cm). In search, it uses 1 MHz pulses with lengths of 1.5 or 2.0 ms, and in track it uses six different 5 MHZ bandwidth pulses with lengths between 0.15 and 1.5 ms. The radar also has two 1.0 ms, 25 MHz bandwidth pulses used for ionospheric compensation.
milstar: https://www.icomamerica.com/en/products/amateur/hf/9100/default.aspx https://www.icomamerica.com/en/products/amateur/hf/9100/default.aspx 1200 mhz triple conversion 24 bit ADC
milstar: https://www.custommmic.com/resources/cmd283c3-1218.pdf https://www.custommmic.com/cmd283c3/
milstar: Mixer https://www.analog.com/media/en/technical-documentation/data-sheets/ADL5365.pdf +20 dbm input on 50 ohm ! 100 milliwatt on 50 ohm = u*u/8Rn ===== 6.3 volt peak to peak on input ! ( rosetka 220volt peak to peak 220*2*square root from 2 =220*2.82=620volt peak to peak ) =========================== https://www.analog.com/media/en/technical-documentation/data-sheets/hmc785.pdf he HMC785LP4 1db compression point 26dbm
milstar: https://www.analog.com/media/en/technical-documentation/application-notes/high_ip3_mixers_for_cellular_applications.pdf
milstar: https://ww2.minicircuits.com/app/AN00-009.pdf
milstar: https://nardamiteq.com/docs/MITEQ_Mixer_Question_Answers.pdf
milstar: http://rfic.eecs.berkeley.edu/ee242/pdf/Module_5_3_MixerDesign.pdf
milstar: http://amsacta.unibo.it/1258/1/GA051750.PDF
milstar: http://vko.forum24.ru/?1-3-0-00000201-000-240-0
milstar: https://www.analog.com/media/en/technical-documentation/data-sheets/5551fa.pdf
milstar: The superior performance of this mixer is ideally suited for a wide range of mission-critical, high performance applications that are exposed to strong interference sources such as multi-carrier GSM, 4G LTE and LTE-Advanced multimode basestations, point-to-point backhauls, military communications, wireless repeaters, public safety radios, VHF/UHF/white-space broadcast receivers, radar and avionics. The LTC5551 offers very high linearity of +36dBm IIP3, (input third-order intercept), and low 9.7dB noise figure comparable to the highest IIP3 passive mixers available. Unlike passive mixers which typically have 7dB to 9dB of conversion loss, the LTC5551 boasts 2.4dB of conversion gain, substantially improving receiver dynamic range. The device also has broad RF frequency range capability, operating from 300MHz to 3.5GHz. https://www.powersystemsdesign.com/articles/linears-36dbm-iip3-downconverting-mixer-boasts-a-2-4db-conversion-gain/6/883
milstar: The LTC5551 consists of a high linearity double-balanced mixer core, IF buffer amplifier, LO buffer amplifier and bias/enable circuits. See the Block Diagram section for a description of each pin function. The RF and LO inputs are single-ended. The IF output is differential
milstar: https://www.fairviewmicrowave.com/images/productPDF/FMMX9000.pdf
milstar: https://www.analog.com/media/en/technical-documentation/data-sheets/2107fb.pdf https://www.analog.com/media/en/technical-documentation/data-sheets/238718fa.pdf https://pdfserv.maximintegrated.com/en/an/AN1929.pdf
milstar: https://www.maximintegrated.com/en/app-notes/index.mvp/id/5429
milstar: High resolution analog to digital converters (ADCs) are rare commodities. They serve very specific markets that demand high dynamic range and good measurement accuracy, helping to provide accurate representations of real world signals in challenging noise environments. Up until recently, this market was largely served by delta-sigma ADCs, which are specialized devices that must be oversampled, resulting in very slow data output rates. This article introduces a new successive approximation register (SAR) ADC that combines both high resolution with high sample rate and exceptional 24-bit dynamic range, exceeding the dynamic range and measurement accuracy of its peers. The following applications are examples of how this high dynamic range can be put to good use. A medical application, like an encephalograph, may require the gathering of signals in the presence of high levels of noise; the electrical activity in a cell when stimulated, known as the action potential, can range from 10uV to 100mV at frequencies from 100Hz to 2kHz. If the signals are buried in the noise you need to average the samples to resolve the signal, requiring an ADC with high dynamic range. Seismology and seismic exploration are other demanding applications with common requirements. Seismometer and accelerometer signals can have a dynamic range of 140dB and frequencies up to 100Hz. The SNR of seismic signals received by sensors is very low due to absorption and attenuation by subsurface and deep layers during signal propagation. This creates a real challenge to measure these signals. A gas sensor must be able to detect very low concentrations of gas, alarming at detection levels as low as 0.5ppm. High accuracy and wide dynamic range is vital for this application to ensure toxic chemicals are detected swiftly, but also ensure alarms are not activated unnecessarily. Broader trends are also raising the data conversion bar. The move towards portable devices is resulting in increasingly complex data conversion tasks migrating to battery-powered devices. Designers must develop solutions using less space while simultaneously minimizing power consumption. For data conversion tasks, each of the common ADC architectures brings with it a list of advantages and drawbacks. Data Converter Architectures Analog-to-digital converter design mostly involves a series of compromises. For converters, a lot depends on the primary goal: high resolution, high speed, or low power consumption. Note: you can't necessarily pick all three! To cover the full spectrum of application requirements, multiple ADC architectures have appeared over the years, but there are three primary architectures in use today. The successive approximation register (SAR) architecture traditionally has been the workhouse, "go-to" architecture for mainstream analog-to-digital converter applications with low frequency signals. It provides the transition between high resolution, low speed delta-sigma architectures, and the high speed, lower performance, pipeline architecture. They are usually lower cost compared to pipelined ADCs, and consume a modest amount of power. The SAR converter shows no latency between successive conversions, so it is ideal for sampling multiplexed or non-periodic signals. Pipeline converters use a multi-stage sequential pipeline architecture to increase sampling speed. They rule the market at very high sample rates for acquiring wide signal bandwidths or signals at higher input frequencies, and on a per sample basis consume less power when compared to fast SAR ADCs. They're unsuited to handle multiplexed or non-periodic inputs because they have to "flush the pipe" every time the source changes, which adds considerable latency. The main rival to the SAR ADC for higher-resolution applications has been the delta-sigma converter; this relies on a delta-sigma modulator and a digital decimation filter. This architecture is slow compared to the SAR and is not as accurate. Most importantly, the noise spectrum of a delta-sigma ADC includes vibrating noise tones whereas the SAR ADCs noise floor has a uniform power spectral density. This makes SAR ADCs better for detecting tones or vibrations at incredibly low levels. Introducing the LTC2380-24 Despite its disadvantages, the relatively slow delta-sigma architecture has been the only option for high-resolution applications because SAR converters have traditionally not been available at resolutions above 18 bits. Recently, Linear Technology introduced the LTC2380-24, a SAR converter that combines high resolution (24-bits) with high sample rate (up to 2Msps). It's the flagship member of Linear Technology's LTC2380 family, which includes the 20-bit 1Msps LTC2378-20, the 18-bit 1.6Msps LTC2379-18 and the 16-bit 2Msps LTC2380-16 among others. All these parts come in the MSOP-16 and 4mm by 3mm DFN packages, and are pin-compatible. Part Number Package Temp LTC2380CDE-24#PBF 4x3 DFN-16 Commercial LTC2380CDE-24#TRPBF 4x3DFN-16 Commercial LTC2380CMS-24#PBF MS-16 Commercial LTC2380CMS-24#TRPBF MS-16 Commercial LTC2380IDE-24#PBF 4x3DFN-16 Industrial LTC2380IDE-24#TRPBF 4x3 DFN-16 Industrial LTC2380IMS-24#PBF MS-16 Industrial LTC2380IMS-24#TRPBF MS-16 Industrial The 24-bit precision, fast 2Msps sample rate and unparalleled ±0.5ppm (typ) linearity enables the LTC2380-24 to resolve very low-level input signals in high dynamic range applications such as ECG/EEG. The LTC2380-24 includes additional features that help simplify common design problems, such as a built-in digital filter and digital gain compression for single supply operation. Detailed technical specifications appear on the LTC2380-24 product page; this article will discuss some of the special features of the part and how they benefit target applications, as well as touch on a couple of application details. Digital Filtering For Averaging Many applications, such as seismic exploration, require the accurate measurement of a weak low-frequency signal in the presence of broadband noise. Oversampling the signal at a rate much higher than Nyquist, then averaging the result of multiple conversions, reduces the effect of this uncorrelated noise. Oversampling increases the effective dynamic range of the ADC by spreading out the noise across a wider bandwidth, thus reducing the noise spectral density in the bandwidth of interest. This also reduces the complexity of the front-end anti-aliasing filter, which results in less power being consumed and less noise and distortion being introduced. The LTC2380-24 features an integrated digital averaging filter that can provide this function without any additional hardware, simplifying the design and providing a number of unique advantages. The high sample rate of the LTC2380-24 makes this an option for many applications. The benefit to the user is that this frees up valuable resources in the processor to perform other tasks, while the averaged data can be transferred at much slower data rates (as low as 2Msps). The digital averaging filter used in the LTC2380-24 is known as a SINC1 filter. It can average blocks of conversions from as few as N = 1 to as many as N = 65,536. The results are dramatic, improving the dynamic range from 101dB at 1.5Msps, to true 24-bit performance of 145dB at 30.5sps as shown in figure 1. With 40.9nVrms/ √Hz noise spectral density, the LTC2380-24’s dynamic range in 1Hz of bandwidth is over 158dB! https://www.arrow.com/en/research-and-events/articles/24-bit-2msps-sar-adc-takes-dynamic-range-to-a-new-level
milstar: http://www.lucabarbi.it/product/winradio_pdf/G35DDCbrochure.pdf
milstar: For example, Figure 25.1 shows a simplified block diagram of the receiver front end of a typical radar system that would have been designed around 1990. Note that this system incorporated analog pulse compression (PC). It also included several stages of analog downconversion, in order to generate baseband in-phase (I) and quadrature (Q) signals with a small enough bandwidth that the ADCs of the day could sample them. The digitized signals were then fed into digital doppler/MTI and detection processors http://www.jocoleman.info/pubs/papers/SkolnikCh25.pdf
milstar: https://www.kit-e.ru/assets/files/pdf/2008_09_22.pdf
milstar: http://www.ti.com/lit/wp/snaa107/snaa107.pdf Processing gain can also be calculated by finding the noise floor of the ADC in dBm/Hz. With an IF of 244 MHz at -1 dBFS, the SNR of the ADC12DL080 is 65 dBFS or -55 dBm since full scale is +10 dBm into 50 W . To trans- late into dBm/Hz, take 10 * LOG (Fs/2) and subtract it from -55 dBm. 10 * LOG (39 MHz) = 75.9 dB, therefore the ADC12DL080 noise floor in this example is -130.9 dBm/Hz. Now if the channel bandwidth is 200 kHz, add back 10 * LOG (200 kHz) or 53 dB to get a noise floor of -77.9 dBm in 200 kHz, which is 22.9 dB better than the ADC by itself. Translating back to dBFS, the total SNR is 87.9 dB in a 200 kHz channel. This is similar to decreasing the resolution bandwidth on a spectrum analyzer; the noise floor has been lowered, but the ADC’s resolution has not been increased
milstar: https://arxiv.org/pdf/0807.0349.pdf time stretch ADC BW 10 ghz ENOB 7 bit ,SFDR 53 db
milstar: Note that the increased sampling rate does not dire ctly improve ADC resolution, but by providing more samples, this technique more accurately tracks th e input signal by better utilizing the existing ADC dynamic range. It should be clear that oversampling by itself improves the digital representation of the signal only down to the physical dynamic range limit (minimum step size) of the ADC https://www.microsemi.com/document-portal/doc_view/131569-improving-adc-results-white-paper
milstar: Analog Devices AD9467 16-bit ADC 2010 100 dBFS SFDR at 100 MHz at 160 MSPS (@ −1 dBFS) 60 fs rms Jitter 1.32W total power dissipation including drivers, The device is fabricated on .18 silicon germanium BiCMOS
milstar: A heterodyne receiver includes a first mixer (LO1) that converts the RF waveform to a first intermediate frequency (IF) signal ( Figure 1 ). This IF signal can either be digitized or fed to a second mixer (LO2) to convert the desired signal to an even lower IF. Converting the signal to a lower IF frequency takes advantage of the ADC's better noise and linearity performance, which is typically achieved at lower frequency inputs. A technique known as subsampling is used to digitize the real bandpass signal at a rate that meets the Nyquist criterion for the signal's bandwidth, but not for its absolute frequency. Using this technique, an ADC digitizes the real signal, which is then converted to its complex components in the digital domain using digital signal processing (DSP) methods. Advantages to this technique include reduced hardware complexity and cost. These advantages are possible because the subsampling method performs part of the downconversion task. However, this architecture requires an ADC with higher clocking speed and larger overall dynamic range (i.e., lower noise and higher linearity). Despite the benefits that subsampling techniques provide, one important drawback is noise aliasing. Such aliasing reduces the equivalent ADC SNR performance if the input signal is not sufficiently band limited, allowing noise in the alias bands to be digitized and converted to baseband along with the desired signal. https://pdfserv.maximintegrated.com/en/an/AN3717.pdf
milstar: https://www.teledyne-e2v.com/shared/content/resources/File/documents/broadband-data-converters/EV12AQ600/1203D_EV12AQ600%20preliminary%20datasheet%20(web).pdf in 4 channel mode 1 N zone Fin 778 mhz ,-1 dbfs SFDR 73.7 dbfs SNR 54.3 dbfs,averaged simul sampled 59.4 dbfs SINAD 53.8 averaged 59 ENOB 8.6 averaged 9.5 ========= 2 chan mode interleaved SFDR -64 SNR 53.9 SINAD 53.2 ENOB 8.6 ========== 1chan SFDR 63 SNR 53.9 SINAD 52.8 ENOB 8.5
milstar: https://www.teledyne-e2v.com/shared/content/resources/File/documents/broadband-data-converters/EV12AD550/EV12AD550B%20Datasheet.pdf
milstar: https://www.analog.com/media/en/technical-documentation/data-sheets/ad9697.pdf 14 bit 1300 msps APPLICATIONS Communications Diversity multiband, multi mode digital receivers 3G/4G, TD -SCDMA, W -CDMA, GSM, LTE General- purpose software radios Ultra wideband satellite receiver ============= 1.36 V p-p SFDR 10 mhz -81 dbfs 172 -81 340 -80 -------------- SINAD -64 =========== ENOB 10.3 ========= Noise Density -152.6
milstar: https://www.analog.com/media/en/technical-documentation/data-sheets/AD9213.pdf 12 bit ,10.25 GSPS Fin 1000 mhz SNR 55.1 SINAD 55 ENOB 8.8 SFDR 71 Input buffered pipelined ADC.
milstar: https://www.analog.com/media/en/technical-documentation/data-sheets/AD9695.pdf
milstar: http://www.astrosurf.com/luxorion/Radio/elecraft-k3-qst-review.pdf
milstar: https://www.analog.com/media/en/technical-documentation/application-notes/AN-1279.pdf https://www.analog.com/media/en/technical-documentation/data-sheets/AD7960.pdf https://www.analog.com/media/en/technical-documentation/data-sheets/AD7626.pdf 16 bit ,10 msps Fin 100 khz SFDR 104.5 db ,SINAD 91 db https://www.analog.com/media/en/technical-documentation/data-sheets/238718fa.pdf 18 bit ,15 msps SAR ,8.192 Volt peak to peak input Fin 1 mhz , 2khz 200 khz SFDR 102 db, 119 109 SINAD 94.5 95.7 95.6
milstar: https://www.eham.net/ehamforum/smf/index.php?topic=122511.0 The pictured IC is the LTC2387-18 which is an 18-bit 15 Msps ADC. Yaesu's ads for this new rig in QST says it uses direct sampling, but it also says it has a 9MHz IF.
milstar: https://qrznow.com/wp-content/uploads/2018/11/FTDX101DMP.pdf
milstar: We could use stretch processing for track because we already know range fairly well but want a more accurate measurement of it Stretch pro cessing relieves the signal processor bandwidth problem by giving up all rang e processing to obtain a narrow -band signal processor http://www.ece.uah.edu/courses/material/EE710-Merv/Stretch_11.pdf We will assume baseband processing in these discussions. In practice the mixer output will be at some intermediate frequency (IF). ========================== The signal could be brought to base - band using a synchronous detector or, as in some modern radars, by using IF sampling (i.e. a digital receiver) . In either case, the effective ADC rate (the sample rate of the complex, digital base - band signal) will be as derived here. https://www.ll.mit.edu/sites/default/files/page/doc/2018-05/19_2_4_Stambaugh.pdf
milstar: 18 of frequencie s. The SNR is improved by this digital-filtering process since the power of the residual error is decreased by filtering. The SFDR specification for the ADC is important because a spurious component still may fall within the bandwidth of the digital filter; hence, the SFDR, unlike the SNR, does not necessari ly improve by the digital-filtering process. However, several techniques are available to improve the SFDR. Dithering (discussed in Section 2.2) im proves the SFDR of ADC’s. Additionally, postdigitization-processing techniques such as state variable compens ation [13], phase-plane compensation [14], and projection filtering [15] have been used to improve SFDR. http://www.amwindow.org/misc/pdf/DigitalRXConcepts.pdf
milstar: http://www.ti.com/lit/an/slaa594a/slaa594a.pdf
milstar: https://www.w8ji.com/cw_bandwidth_described.htm
milstar: Integrated mixers can be designed to high tolerances. Enabled by integrated matching techniques, such mixers may incur lower costs by taking advantage of silicon processes. As noted by Tom Schiltz, design section leader of high-frequency products for Linear Technology, “Advanced silicon-process technologies offer higher speed and a wider operating frequency. But they come at the expense of lower breakdown voltages, which can limit mixer IIP3 and input-signal handling capability.” He also warns that “integrated mixers are limited by the parasitics of packaging technologies available today and the electrostatic-discharge (ESD) circuits that are required to protect the device.” https://www.mwrf.com/active-components/rf-mixers-pine-linearity-and-dynamic-range
milstar: Рис. 1. Архитектура тракта приема с двойным преобразованием частоты Полосовой ВЧ фильтр (Band Select Filter) ПФ1, предшествующий малошумящему усилителю МШУ (low noise amplifier) уменьшает внеполосные сигналы, а также уровень помех по зеркальному каналу совместно с фильтром ПФ2 (image reject filter). Затем весь спектр преобразуется вниз по частоте на фиксированную промежуточную частоту (Intermediate Frequency, IF) с использованием перестраиваемого гетеродина РЧ ГУН. Зеркальный сигнал и другие нежелательные продукты преобразования уменьшаются далее до приемлемого уровня, с помощью внешнего фильтра ФПЧ1 перед еще одним преобразованием вниз по частоте. Выбор рабочего канала обычно осуществляется, фильтром ПЧ2 (Channel Select Filter) после окончательного преобразования вниз. Это ослабляет требования к динамическому диапазону следующих блоков. От правильного выбора значения промежуточных частот зависят получаемые величины селективности и чувствительности приемника. Второе преобразование вниз по частоте в современных трактах приема обычно происходит в квадратурных схемах, чтобы облегчить цифровую обработку синфазных и квадратурного сигналов I и Q. В приемнике с двойным преобразованием частоты существенно снижаются требования к элементам фильтрации. Супергетеродинная архитектура приемного тракта считается наиболее надежной, так как в ней высокие значения селективности и чувствительности могут быть достигнуты надлежащим выбором значений ПЧ и параметров фильтров. Эффекты смещения постоянной составляющей (DC offset) и утечки (leakage), более подробно рассмотренные далее, не влияют на характеристики приемника из-за использования нескольких шагов преобразования. Однако, достижение высоких значений параметров и характеристик приемника приводит к увеличению стоимости устройства и его размеров. Это происходит за счет применения внешних высокодобротных полосовых фильтров, необходимых для подавления зеркального канала и выбора рабочего канала. Так как выбор рабочего канала происходит в первом каскаде ПЧ, перестраиваемый гетеродин требует качественного выполнения и использования внешнего колебательного контура для достижения хорошей характеристики по шумам. Указанные факторы затрудняют полную интеграцию приемопередатчика в единственной микросхеме. https://www.rlocman.ru/shem/schematics.html?di=40226
milstar: Приемники с низкой ПЧ Стремление разработчиков к созданию полностью интегрированного высококачественного РЧ блока с элементами внутрикорпусной полосовой фильтрации привела к появлению архитектуры приемника с низкой ПЧ (Low-IF receivers). Основная цель ее использования состоит в том, чтобы защитить приемник от смещения постоянной составляющей, являющегося главным недостатком приемников прямого преобразования, при сохранении основного достоинства таких приемников – устранения высокодобротных фильтров ПЧ. В этой архитектуре величина низкочастотной ПЧ составляет обычно сотни кГц, так что в ней может быть применен низкодобротный ФНЧ выбора рабочего канала. https://www.rlocman.ru/shem/schematics.html?di=40226
milstar: Как следует из названия, вместо непосредственного преобразования сигнала на нулевую частоту и подачи этого сигнала на информационный блок, частота гетеродина слегка сдвинута от несущей РЧ, обычно на один – два канала.
milstar: Широкополосные приемники с двойным преобразованием частоты В последнее время разработчики стали проявлять интерес к архитектуре широкополосного приемника с двойным преобразованием частоты (Wideband double-IF receiver), в котором объединена архитектура приемника с нулевой ПЧ и традиционного супергетеродина, позволяющая по мнению ряда разработчиков оптимизировать потребление мощности и характеристики устройства [5]. Блок-схема широкополосного приемника с двойным преобразованием частоты показана на рис. 12. Эта структура похожа на супергетеродин, в котором используется несколько каскадов ПЧ, а первая ПЧ находится в области сотен МГц. https://www.rlocman.ru/shem/schematics.html?di=40226
milstar: Развитие техники и технологии цифровых ИС привело к тому, что заключительное смешивание и фильтрация, осуществляемые в каскадах ПЧ, могут производиться уже в цифровой области [4,7,8]. В приемниках с цифровой ПЧ (Digital IF receiver) происходит оцифровавание непосредственно сигнала ПЧ. В качестве ПЧ гетеродина используется прямой цифровой синтезатор частот DDS (Direct Digital frequency Synthesizer) называемый иногда генератором с цифровым (программным) управлением NCO (Numerically Controlled Oscillator). Это устройство реализовано полностью с использованием цифровой техники и рядом фирм выполняется в виде специализированной ИС. Генератор формирует цифровые выборки двух синусоид с точным сдвигом по фазе на 90 градусов (рис. 15). https://www.rlocman.ru/shem/schematics.html?di=40226
milstar: Приемник супергетеродинного типа с цифровой промежуточной частотой https://studref.com/480548/tehnika/priemnik_standarta_wimax#241
milstar: В приемниках узкополосного сигнала с достаточно высокой несущей частотой в ряде случаев приходится использовать не только двойное преобразование частоты, но и тройное. ============================ При этом принципы формирования требований к дополнительным блокам не отличаются от рассмотренных ранее для супергетеродинного приемника с двойным преобразованием частоты. http://digteh.ru/WLL/PrmDvPreobr.php В схеме супергетеродинного приемника с двойным преобразованием частоты приходится точно так же тщательно рассчитывать параметры каждого блока, как и в рассмотренной ранее схеме супергетеродинного приемника. При приеме цифровых видов сигнала приходится учитывать положение частоты первого и второго гетеродинов (выше или ниже частоты входного сигнала), так как это может привести к изменению направления вращения вектора квадратурного сигнала.
milstar: 1. Для получения лучшей селективности по зеркальному каналу промежуточная частота должна быть выше принимаемого диапазона частот Выбрав промежуточную частоту выше частот рабочего диапазона, можно в приемнике с диапазоном 2-30 МГц использовать эллиптический фильтр нижних частот с частотой среза, например, 31 МГц. В этом случае помехи с частотами выше рабочего диапазона ослабляются на 80 дБ, а селективность по зеркальному каналу не зависит от частоты принимаемых сигналов. Тот же фильтр обеспечит ослабление излучения гетеродина, что позволяет располагать несколько приемников на близком расстоянии друг от друга. Когда промежуточная частота равна, например, 40 МГц, гетеродин должен перекрывать диапазон 42-70 МГц (в приемнике с диапазоном 2-30 МГц); следовательно, коэффициент перекрытия составляет менее 1:2. При этом значительно упрощается конструкция гетеродина и уменьшается вероятность того, что взаимодействие гармоник гетеродина с входными сигналами в преобразователе частоты приведет к образованию помех, попадающих в полосу пропускания приемника. http://www.radioman-portal.ru/pages/699/ 2. Использование раздельных каскадов для АРУ и для усиления с целью уменьшения искажении. В прошлом электронные лампы использовались одновременно и для усиления, и для АРУ. Однако из-за нелинейности ламповых характеристик при поступлении напряжения АРУ возникали интермодуляционные искажения. То же самое имеет место и при использовании биполярных и полевых транзисторов. Если же усиление и АРУ осуществлять в раздельных каскадах, то можно обеспечить оптимальный режим каждого из них. Так, например, для АРУ можно использовать аттенюатор на pin-диодах. включенный между входным фильтром нижних частот и ВЧ-усилителем, как показано на рис.1. Диодный аттенюатор должен иметь постоянные входные и выходное импедансы, так как в противном случае всякое изменение импеданса нагрузки приведет к изменению характеристик фильтра, а изменение импеданса источника, работающего на усилитель, вызовет в нем изменение шумов и искажений. На рис. 2 показан аттенюатор, представляющий собой обычный двойной T-мост на pin-диодах. Входной и выходной импедансы такого аттенюатора поддерживаются неизменными. С этой целью используется дифференциальный усилитель, который обеспечивает соответствующее перераспределение токов в выводах аттенюатора (сумма коллекторных токов должна быть неизменной). Получение прямоугольной частотной характеристики УПЧ при использовании узкополосных полосовых фильтров всегда представляло серьезную проблему. В новой схеме с двойным инвертированием спектра входного сигнала можно применить фильтры нижних частот, при этом крутизна ската частотной характеристики УПЧ не зависит от полосы пропускания. Дополнительным преимуществом фильтров нижних частот является в два раза меньшее по сравнению с полосовыми фильтрами время установления. Это устраняет нежелательные колебания в фильтрах в случае приема импульсных сигналов. Сущность способа поясняется схемой (рис.6). Селективность приемника определяется главным образом трактом второй промежуточной частоты 525 кГц. Полоса пропускания по второй промежуточной частоте и, следовательно, полоса пропускания приемника в целом могут устанавливаться в пределах 150 Гц-12 кГц. При этом выбор полосы пропускания осуществляется не заменой фильтра, а регулировкой частотного сдвига между двумя гетеродинами. Сигнал 525 кГц с максимальной шириной спектра, например ±6 кГц (510-531 кГц), поступает на преобразователь частоты вначале с частотой гетеродина 467 кГц, в результате чего образуется сигнал, занимающий полосу частот от 52 (525-6-467) до 64 кГц (525+6-467). Результирующий сигнал поступает в кварцевый фильтр нижних частот, частотная характеристика которого имеет резкий спад на частоте 64 кГц (этот спад образует один из фронтов частотной характеристики УПЧ). Указанный фильтр с фиксированной частотой среза настраивается только один раз. Затем спектр сигнала с полосой 52-64 кГц вновь переносится на среднюю частоту 525 кГц и вновь поступает на преобразователь с частотой гетеродина 583 кГц. При этом сигнал возвращается в диапазон 52-64 кГц, но с инвертированным спектром (составляющие спектра, находившиеся ранее у границы полосы пропускания 64 кГц, сейчас находятся на 12 кГц ниже этой границы). Фильтр с частотой среза 64 кГц подавляет составляющие сигнала, находившиеся при первом преобразовании у границы 52 кГц. Полученный таким образом сигнал, отфильтрованный с высокой селективностью, вновь переносится по спектру на частоту 525 кГц и детектируется. Следует отметить, что фронты частотной характеристики УПЧ сохраняются неизменными, а ширина полосы уменьшается регулировкой частотного сдвига между двумя гетеродинами. Так, например, при ширине полосы пропускания 2 кГц гетеродины настроены на частоты 462 кГц (525+1-64) и 588 (525-1+64). В связи с тем, что границы полосы пропускания формируются фильтром нижних частот, частотная характеристика близка к прямоугольной даже при ширине полосы пропускания 150 Гц. Описываемый способ обеспечивает симметрию фазовой характеристики или характеристики групповой задержки относительно средней частоты. Кварцевые или механические фильтры, обычно используемые в УПЧ, являются чебышевскими фильтрами с нелинейной фазовой характеристикой. В то же время фильтры нижних частот бесселевского типа могут обеспечить требуемую линейность. http://www.radioman-portal.ru/pages/699/
milstar: Yaesu FT-1000 received frequency 100 khz-30 mhz Quad conversion ============== 1 IF 73.62 mhz 2 IF 8.215 mhz 3 IF 455 khz 4 IF 100 khz http://radiomanual.info/schemi/YAESU_HF/FT-1000_user.pdf
milstar: http://www.ti.com/lit/ug/tidubs6/tidubs6.pdf ADC Copyright © 2016, Texas Instruments Incorporated 1 TIDUBS6 –May 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated RF Sampling S-Band Radar Receiver TI Designs RF Sampling S-Band Radar Receiver
milstar: ICOM R9500 Quad conversion professional communication receiver http://www.icom.co.jp/world/support/download/brochure/pdf/Receivers.pdf
milstar: https://www.icomamerica.com/en/products/amateur/receivers/r8600/default.aspx 1100 -3000 mhz 3 conversion + 14 bit 122 msps ADC in demodulation
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