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Operazionnie ysiliteli ,ZAP/AZP & (ïðîäîëæåíèå)
milstar: 1941: First (vacuum tube) op-amp An op-amp, defined as a general-purpose, DC-coupled, high gain, inverting feedback amplifier, is first found in US Patent 2,401,779 "Summing Amplifier" filed by Karl D. Swartzel Jr. of Bell labs in 1941. This design used three vacuum tubes to achieve a gain of 90dB and operated on voltage rails of ±350V. ###################################################### It had a single inverting input rather than differential inverting and non-inverting inputs, as are common in today's op-amps. Throughout World War II, Swartzel's design proved its value by being liberally used in the M9 artillery director designed at Bell Labs. ######################################################################### This artillery director worked with the SCR584 radar system to achieve extraordinary hit rates (near 90%) that ####################################################################### would not have been possible otherwise.[3] ########################### http://en.wikipedia.org/wiki/Operational_amplifier
milstar: September 2014 GSPS Data Converters to the Rescue for Electronics Surveillance and Warfare Systems! By Analog Devices http://www.mpdigest.com/issue/Articles/2014/Sept/Analog/default.asp
milstar: Figure 5. The output spectrum of the AD9625, clocked at 2.5 GSPS and with an input tone close to 1 GHz. (a) Sequential three-way interleaving; SNR = 60 dBFS, the SFDR = 72 dBc is limited by the third harmonic, near 500 MHz; however, a number of interleaving spurs are visible all across the spectrum. (b) Three-way interleaving with random channel shuffling; SNR = 58 dBFS, while the SFDR = 72 dBc is still set by the third harmonic, all the interleaving spurs have been eliminated by spreading their power over the noise floor. http://www.analog.com/library/analogDialogue/archives/49-07/interleaving_adcs.html The AD9625 is a 12-bit/2.5 GSPS three-way interleaved ADC. The mismatches between the three channels are calibrated in order to minimize the interleaving spurs. An example of its output spectrum with an input close to 1 GHz is depicted in Figure 5(a). In this spectrum, besides the ~1 GHz input tone, it is possible to see the channels’ 2nd and 3rd harmonic distortion near 500 MHz and the 4th harmonic distortion near the fundamental. The interleaving mismatch calibration substantially minimizes the power of the interleaving spurs and a large set of additional residual small spurious tones is visible across the entire spectrum. In order to further reduce such residual spurious content, channel randomization is introduced. A fourth calibrated channel is added and the four channels are then three-way interleaved in randomly changing order by intermittently swapping one of the interleaved channels with the fourth one. One can liken that to a juggler playing with three Skittles up in the air while a fourth one is swapped in every so often. By doing so, the residual interleaving spurious power is randomized and spread out over the noise floor. As shown in Figure 5(b), after channel randomization, the interleaving spurs have nearly disappeared, while the power of the noise has marginally increased, hence degrading the SNR by 2 dB. Note, of course, that while the second spectrum shown in Figure 5(b) is considerably cleaner of distortion tones, the shuffling cannot affect the 2nd, 3rd, and 4th harmonic since these aren’t interleaving spurs.
milstar: Handling 30 differential LVDS pairs per ADC can be challenging to route and maintain matched lengths on a system layout. The equivalent data can be sent with only six or eight differential lanes using JESD204B, a high speed serialize/deserialize (SERDES) standard designed specifically for converter interfaces. JESD204B provides a means to output data at high speeds on fewer data lines without the matched timing board complexities of many high speed LVDS lanes. Since the data sent over JESD204B is framed based on an embedded clock and control characters, the routing of the lower count serial lanes is much more forgiving of timing skew than LVDS, as seen in Figure 2. This removes the need to spend countless hours working to tweak output timing on every I/O of the system PCB. In addition, JESD204B offers informational “control bits” of auxiliary data that can be appended to each analog sample to help characterize the downstream processing. In this fashion, trigger time stamping and overrange conditions can be tagged per sample so that a back-end FPGA can have further intelligence about data alignment and its validity. http://www.analog.com/media/en/technical-documentation/technical-articles/Gigasample-ADCs-Run-Fast-to-Solve-New-Challenges-MS-2702.pdf
milstar: The AD-FMCOMMS6-EBZ platform is a 400MHz to 4.4GHz receiver (1350MHz to 1650MHz with installed filters) in a VITA57-compliant form factor. The receiver integrates the AD9652 dual 16-bit A/D converter, ADL5566 RF/IF dual differential amplifier and ADL5380 quadrature demodulator. A complete design support package is available for the AD-FMCOMMS6-EBZ, and includes schematics, layout files, noise analysis worksheet, FPGA HDL (hardware description language) code, and software drivers. The AD-FMCOMMS6-EBZ incorporates an I/Q demodulator to implement a direct conversion or zero IF architecture in which just one frequency translation is required, compared to a super-heterodyne receiver that must perform several frequency translations. According to ADI, a single frequency translation is advantageous because it "reduces receiver complexity and the number of conversion stages needed, which in turn increases performance and reduces power consumption". The design also avoids image rejection issues and unwanted mixing by adding an amplification stage to maintain the full-scale input to the A/D converter. The image rejection inherent to the I/Q modulation scheme removes the need for an expensive anti-aliasing filter. The on-board local oscillator and converter clock share the same reference signal to prevent smearing. The AD-FMCOMMS6-EBZ receiver development platform incorporates a full direct-receive signal chain path and has a bandwidth of 220MHz with a pass-band flatness of +/- 1.0 dB. The RF input range of the ADL5380 demodulator is 400MHz to 6GHz and is powered by a single 5V supply. The ADL5566 4.5GHz dual differential amplifier is optimized for IF and dc applications and provides a gain of 16dB. The AD9652 dual 16-bit, 310MSPS A/D converter achieves the industry’s lowest noise at the highest speed; this level of performance enables target identification at a much longer range. The SNR and SFDR measured at an IF of 145MHz are 64dB and 78dBc, respectively. http://www.electronicsweekly.com/news/products/rf-microwave-optoelectronics/direct-conversion-receiver-means-smaller-radars-says-adi-2014-12/
milstar: The AD9680 completes the chain and is one of the latest high speed converters. Based on 65 nm CMOS, the device supports sampling at up to 1 GSPS at a resolution of 14 bits. Using higher sample rates and the bandwidths of gigasample converters, the AD9680 potentially supports undersampling an IF in excess of 1 GHz. This supports the continued trend of moving the digital conversion point of the system closer to the antenna and increasing the flexibility of the system. The device not only provides industry-leading SFDR and SNR but also incorporates digital downconversion (DDC) signal processing, to provide customizable output bandwidths. The digital signal processing configurability of the AD9680 ADC enables the device to support wideband surveillance, as well as narrow-band functionality. With the incorporated DDC disabled and bypassed, it can support an instantaneous surveillance bandwidth in excess of 500 MHz. --------------------------------------------------- Utilizing the DDCs, the digital numerically controlled oscillator (NCO) can be set to digitally mix a narrow-band IF to baseband before configurable decimation filters reduce the data rate, supporting output data bandwidths down to 60 MHz when the device is operated at the maximum ADC sample rate -------------------------------------------------------------------- . Thedigital signal processing improves the SNR of the system for the lower bandwidth, again supporting the flexibility needed for a configurable wideband and narrow-band signal chain. http://www.analog.com/library/analogDialogue/archives/49-06/Multifunction_Dilemma.pdf
milstar: AD9680 1.2 GSPS 2*14 bit Noise density = −154 dBFS/Hz at 1 GSPS SFDR = 85 dBFS at 340 MHz, 80 dBFS at 1 GHz SNR = 65.3 dBFS at 340 MHz (AIN = −1.0 dBFS), 60.5 dBFS at 1 GHz (AIN = -1.0 dBFS) http://www.analog.com/en/products/analog-to-digital-converters/high-speed-ad-10msps/high-if-ad-converters/ad9680.html#product-overview
milstar: RF Sampling 4-GSPS ADC With 8-GHz DC-Coupled, Fully-Differential Amplifier Reference Design http://www.ti.com/lit/ug/tiduaz9/tiduaz9.pdf SFDR 1747 mhz -61 dBFS SINAD 1747 mhz -50.37 dBFS ------------------------- SFDR 197.77 mhz -67.34 dBFS SINAD 197.77 mhz -53.65 dBFS
milstar: ADC12D1800RF 12-Bit, Single 3.6 GSPS RF Sampling ADC Resolution: 12 Bits 1800 MSPS Dual ADC – Interleaved 3.6 GSPS ADC (all typical) • New DESCLKIQ Mode for High Bandwidth, High • IMD3 (Fin = 2.7GHz at -13dBFS) –62 dBc • Noise Floor Density -155.0 dBm/Hz • • Power 4.29 W – Dual 1800 MSPS ADC, Fin = 498 MHz Inputs • ENOB 9.3 Bits (typ) • SNR 58.1 dB (typ) Adjust • SFDR 71.7 dBc (typ) • Test Patterns at Output for System Debug • Power per Channel 2.15 W (typ) 292 BGA 27*27 mm http://www.ti.com/lit/ds/symlink/adc12d1800rf.pdf
milstar: http://www.e2v.com/shared/content/resources/File/documents/broadband-data-converters/EV12AS350/EV12AS350ATP_PDS.pdf 4 core parallel ,2 value with averaging 4 core Fin 1200 mHZ -1 dBFS over first Nyquist zone ENOB 9/9.5 bit SFDR - 67/67 dBFS SNR - 56.6/60.1 dBFS SINAD -56/59 dBFS
milstar: The Nyquist bandwidth is defined to be the frequency spectrum from DC to fs/2. The frequency spectrum is divided into an infinite number of Nyquist zones, each having a width equal to 0.5fs as shown. In practice, the ideal sampler is replaced by an ADC followed by an FFT processor. The FFT processor only provides an output from DC to fs/2, i.e., the signals or aliases which appear in the first Nyquist zone. http://www.analog.com/media/cn/training-seminars/design-handbooks/36701482523116527500547882375sect4.pdf
milstar: Sampling signals above the first Nyquist( 0.5 Fs- Fs ) zone has become popular in communications because the process is equivalent to analog demodulation. It is becoming common practice to sample IF signals directly and then use digital techniques to process the signal, thereby eliminating the need for the IF demodulator. Clearly, however, as the IF frequencies become higher, the dynamic performance requirements on the ADC become more critical. ---------------------------------------------------------------------- The ADC input bandwidth and distortion performance must be adequate at the IF frequency, rather than only baseband. This presents a problem for most ADCs designed to process signals in the first Nyquist zone, therefore an ADC suitable for undersampling applications must maintain dynamic performance into the higher order Nyquist zones. http://www.analog.com/media/cn/training-seminars/design-handbooks/36701482523116527500547882375sect4.pdf
milstar: Why would we use a DDC over Analogue Techniques? Plainly a DDC is implementing something which could be done in analogue – it’s sometimes good to stop and check why we’d want to do this. The DDC is typically used to convert an RF signal down to baseband. It does this by digitising at a high sample rate, and then using purely digital techniques to perform the data reduction. Being digital gives many advantages, including: • Digital stability – not affected by temperature or manufacturing processes. With a DDC, if the system operates at all, it works perfectly – there’s never any tuning or component tolerance to worry about. • Controllability – all aspects of the DDC are controlled from software. The local oscillator can change frequency very rapidly indeed – in many cases a frequency change can take place on the next sample. Additionally, that frequency hop can be large – there is no settling time for the oscillator. • Size. A single ADC can feed many DDCs, a boon for multi-carrier applications. A single DDC can be implemented in part of an FPGA device, so multiple channels can be implemented – or additional circuitry could also be added. However, there are some disadvantages: • ADC speeds are limited. It is not possible today to digitise high-frequency carriers directly. There are techniques to extend the range of ADCs, but often it is simpler to use analogue circuits to bring the carrier down to an IF that digital circuits can then manage. =============================================== ê ïåðâîé èëè âòîðîé ïðîìåæóòî÷íîé ÷àñòîòå • ADC dynamic range is limited. In many communications systems, the signal’s amplitude can vary greatly. Fast ADCs often only have 12bits of resolution – giving an absolute maximum dynamic range of 72dB. It is often better to use analogue circuits in conjunction with the ADC to implement AGC functions to ensure that this range is best used. In time, more and more systems will use predominantly digital technology. However, the high speeds of many communication systems will ensure that a hybrid approach, using analogue and digital, will be the best route for many systems for a long time to come. The quest for more spectral space will ensure that new systems will use ever higher frequencies, ensuring that analog approaches will be around for a long time to come! http://www.hunteng.co.uk/pdfs/tech/ddctheory.pdf
milstar: Ðàçðåøàþùàÿ ñïîñîáíîñòü ÁÐËÑ Í035 "Èðáèñ-Ý" - 1 ìåòð ýòî ïîëîñà ñèãíàëà 250 Mhz ----------------------------------- AD9680 2*14 bit ,1.25 GSPS http://www.analog.com/media/en/technical-documentation/data-sheets/AD9680.pdf JESD204B (Subclass 1) coded serial digital outputs 1.65 W total power per channel at 1 GSPS (default settings) SFDR at 1 GSPS = 85 dBFS at 340 MHz, 80 dBFS at 1 GHz SNR at 1 GSPS = 65.3 dBFS at 340 MHz (AIN = −1.0 dBFS), 60.5 dBFS at 1 GHz (AIN = −1.0 dBFS)
milstar: SNR is always added in RMS fashion, like power: If the ADC and amplifier plus filter SNRs are equal; the overall SNR is 3 dB less than the ADC. With higher SNR performance from the amplifier and filter, the SNR asymptotically approaches that of the data converter. A 0.1 dB degradation is achieved when the amplifier and filter are optimized for 15 dB better SNR than the ADC. http://www.electronicproducts.com/Analog_Mixed_Signal_ICs/Standard_Linear/Analyzing_ADC_SNR_SFDR_in_high-speed_apps.aspx As previously mentioned, all high-performance ADCs use differential inputs. The key reasons are: 1. Better noise rejection. 2. Double the signal amplitude versus single-ended inputs of the same amplitude. 3. Even-order distortion suppression. Rejecting system noise and effectively doubling the input signal amplitude provide the best SNR performance, while suppression of even-order distortion provides higher SFDR performance. Architectures for driving differential input ADCs Signals in systems are often single ended and must be converted to differential for driving the ADC. There are three ways to do this: 1. Transformers or baluns are excellent at converting single-ended inputs to differential. They require no power, add no noise, and are very linear. The turns ratio can be used to step the voltage up or down. They do not pass dc, but many provide a secondary center tap where the ADC input common-mode-bias can be applied. Their primary drawback is flatness versus frequency. Many times an amplifier is still required and radio frequency (RF)-type amplifiers are often used, especially at higher frequencies, but may require high power to achieve low even-order harmonics. 2. Single-ended op amps can be used in various configurations. One suitable for lower frequencies uses a non-inverting op amp to provide the in-phase output, while also driving an inverting op amp to provide the out-of-phase output. The challenge with this architecture is the two outputs are inherently mismatched and balance cannot be maintained as frequency increases.
milstar: Surveillance and Tracking Radar systems require dynamic range of about 80 dB for the signal. This fact implies that, for this application, with an operating RF frequency of 5 GHz and 14 bit ENOB, the clock jitter should be as low as 0.8 fs and pulse length less than 0.47 ps [4] that is actually very challenging. In this case the digital beam forming concept can be adopted. An array of M digital receivers (up to 100 in new systems) is employed; due to the recombination gain (=10 log10(M)), the requirement on dynamic range is relaxed to 60 dB. http://www.ircphonet.it/research/publication/private_pdf/papers_447.pdf
milstar: The Lynx SAR operates in the Ku-Band anywhere within the range 15.2 GHz to 18.2 GHz, with 320 W of transmitter power. It is designed to operate and maintain performance specifications in adverse weather, using a Sandia derived weather model that includes 4 mm/hr rainfall. It forms fineresolution images in real-time and outputs both NTSC video as well as digital images. The front-end microwave components include a TWTA capable of outputting 320 W at 35% duty factor averaged over the Lynx frequency band, and an LNA that allows an overall system noise figure of about 4.5 dB. http://www.sandia.gov/RADAR/files/spie_lynx.pdf Image formation in all SAR modes is accomplished by stretch processing[2], that is, de-ramping the received chirp prior to digitizing the signal. After the ADCs, presumming is employed to maximize SNR in the image and minimize the load on the subsequent processors. The algorithm used thereafter is an expanded version of the Sandia developed OverlappedSubaperture (OSA) processing algorithm[1], followed by Sandia developed Phase-Gradient Autofocus (PGA)[3]. Either complex images or detected images can be exported to View Manager software.
milstar: Why would we use a DDC over Analogue Techniques? Plainly a DDC is implementing something which could be done in analogue – it’s sometimes good to stop and check why we’d want to do this. The DDC is typically used to convert an RF signal down to baseband. It does this by digitising at a high sample rate, and then using purely digital techniques to perform the data reduction. Being digital gives many advantages, including: Digital stability – not affected by temperature or manufacturing processes. With a DDC, if the system operates at all, it works perfectly – there’s never any tuning or component tolerance to worry about. Controllability – all aspects of the DDC are controlled from software. The local oscillator can change frequency very rapidly indeed – in many cases a frequency change can take place on the next sample. Additionally, that frequency hop can be large – there is no settling time for the oscillator. Size. A single ADC can feed many DDCs, a boon for multi-carrier applications. A single DDC can be implemented in part of an FPGA device, so multiple channels can be implemented – or additional circuitry could also be added. However, there are some disadvantages: ADC speeds are limited. It is not possible today to digitise high-frequency carriers directly. There are techniques to extend the range of ADCs, but often it is simpler to use analogue circuits to bring the carrier down to an IF that digital circuits can then manage. ADC dynamic range is limited. In many communications systems, the signal’s amplitude can vary greatly. Fast ADCs often only have 12bits of resolution – giving an absolute maximum dynamic range of 72dB. It is often better to use analogue circuits in conjunction with the ADC to implement AGC functions to ensure that this range is best used. In time, more and more systems will use predominantly digital technology. However, the high speeds of many communication systems will ensure that a hybrid approach, using analogue and digital, will be the best route for many systems for a long time to come. The quest for more spectral space will ensure that new systems will use ever higher frequencies, ensuring that analog approaches will be around for a long time to come! http://www.hunteng.co.uk/support/ddctheory.htm
milstar: The LTC2217 is a 105Msps sampling 16-bit A/D converter designed for digitizing high frequency, wide dynamic range signals with input frequencies up to 400MHz. The input range of the ADC is fixed at 2.75VP-P. The LTC2217 is perfect for demanding communications applications, with AC performance that includes 81.3dBFS Noise Floor and 100dB spurious free dynamic range (SFDR). Ultra low jitter of 85fsRMS allows undersampling of high input frequencies while maintaining excellent noise performance http://www.linear.com/product/LTC2217 The LTC®2107 is a 16-bit, 210Msps high performance ADC. The combination of high sample rate, low noise and high linearity enable a new generation of digital radio designs. The direct sampling front-end is designed specifically for the most demanding receiver applications such as software defined radio and multi-channel GSM base stations. The AC performance includes, SNR = 80dBFS, SFDR = 98dBFS. Aperture jitter = 45fsRMS allows direct sampling of IF frequencies up to 500MHz with excellent performance. http://www.linear.com/product/LTC2107
milstar: The large bandwidths typical of high-IF sampling A/Ds also allow traditional analog hardware functions to be performed in the digital domain. In many communication systems, the incoming signal is split into I and Q channels which forces the use of two A/D converters. With high bandwidth and high IF converters, the signal can remain within a single channel through the converter and then be split and phase-shifted by subsequent digital circuitry, such as a digital down conversion (DDC) IC. By performing the quadrature demodulation in the digital domain, the split receive path is not needed, thus removing a converter, mixer and the requisite filtering from the architecture. Another benefit of sampling at higher frequencies is that in systems where large bandwidths are not required, the high-IF sampling of the faster converters can be used to gain SNR performance using of decimation. When decimating an A/D converter's output, you essentially throw away a periodic number of samples. Every time the output is decimated by a factor of two, where half the samples are removed, the SNR is improved by three dB. The cost is that the effective sample rate is now halved and, therefore, so is the available bandwidth. For example, suppose a system requires only 20 MHz of bandwidth, but the form factor needs to be small. It is possible with today's fastest 14-bit A/D converter to sample this 20 MHz of bandwidth at 200 MSPS with the center input frequency being 350 MHz, a reasonable output for an RF-to-IF mixing stage. Choosing this frequency for the IF centers the signal band in the converter's Nyquist zone, which spans 300 to 400 MHz. With the signal bandwidth residing in the 340-360 MHz range, the AAF has 40 MHz on either side of the signal to operate. From the contour plots in Figure 1, a converter can achieve 69 dBFS SNR and 73 dBc SFDR at this sample rate and input frequency. http://www.eetimes.com/document.asp?doc_id=1272390 With only 20 MHz of bandwidth to sample, a DDC's numerically controlled oscillator (NCO) could mix the signal to the I and Q bands. In turn, this allows the 200 MSPS sample rate to be decimated by a factor of four to an effective sample rate of 50 MSPS, increasing the SNR by 6 dB to 75 dBFS. Increased signal-chain requirements for high-IF sampling While implementing high-IF sampling solutions can lower component count and save board space, increasing the A/D input frequency does place more stringent demands on the analog signal chain than does low-IF sampling. In the above example, note that placing the center IF at 350 MHz centers the bandwidth in a Nyquist zone and provides 40 MHz of room for the AAF. Although filtering a 20-MHz band centered in a 100-MHz Nyquist zone is generally easier than doing so in one which is 50-MHz wide, doing so at 350 MHz presents a challenge. Op amps tend to degrade in performance at such IF frequencies, http://www.eetimes.com/document.asp?doc_id=1272390
milstar: GSPS ADCs that provide a high wideband SFDR, without the interleaving artifacts that have limited system performance in the past, are now available. The AD9680 is a dual-channel, 14-bit, 1 GSPS ADC that achieves SFDR of 78 dBc with a 1 GHz input. The AD9625 is a 12-bit, 2-GSPS ADC that offers typical wideband SFDR of 80 dBc with a 1 GHz input. SFDR is an important and key performance metric in GSPS and ADCs. Wideband SFDR is typically limited by the second or third harmonic of the fundamental signal. Single monolithic pipeline ADCs and other advanced architectures are advancing a new frontier in high performance GSPS converters. They do not exhibit the interleaving spurs in the frequency domain that have historically been present within ADC architectures in the GSPS space. http://www.analog.com/media/en/technical-documentation/technical-articles/Understanding-Spurious-Free-Dynamic-Range-in-Wideband-GSPS-ADCs-MS-2660.pdf
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