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Operazionnie ysiliteli ,ZAP/AZP & (продолжение)
milstar: 1941: First (vacuum tube) op-amp An op-amp, defined as a general-purpose, DC-coupled, high gain, inverting feedback amplifier, is first found in US Patent 2,401,779 "Summing Amplifier" filed by Karl D. Swartzel Jr. of Bell labs in 1941. This design used three vacuum tubes to achieve a gain of 90dB and operated on voltage rails of ±350V. ###################################################### It had a single inverting input rather than differential inverting and non-inverting inputs, as are common in today's op-amps. Throughout World War II, Swartzel's design proved its value by being liberally used in the M9 artillery director designed at Bell Labs. ######################################################################### This artillery director worked with the SCR584 radar system to achieve extraordinary hit rates (near 90%) that ####################################################################### would not have been possible otherwise.[3] ########################### http://en.wikipedia.org/wiki/Operational_amplifier
milstar: http://cp.literature.agilent.com/litweb/pdf/5989-7830EN.pdf
milstar: http://phobos.iet.unipi.it/~barilla/pdf/FLASH_ADC_tutorial.pdf The first integrated circuit 8-bit video-speed 30-MSPS flash converter, the TDC1007J, was introduced by TRW LSI division in 1979 (References 14 and 15). But as mentioned earlier, full power bandwidths are not necessarily full resolution bandwidths. Ideally, the comparators in a flash converter are well matched both for dc and ac characteristics. Because the sampling clock is applied to all the comparators simultaneously, the flash converter is inherently a sampling converter. In practice, there are delay variations between the comparators and other ac mismatches which cause a degradation in the effective number of bits (ENOBs) at high input frequencies. This is because the inputs are slewing at a rate comparable to the comparator conversion time. For this reason, track-and-holds are often required ahead of flash converters to achieve high SFDR on high frequency input signals. The input to a flash ADC is applied in parallel to a large number of comparators. Each has a voltagevariable junction capacitance, and this signal-dependent capacitance results in most flash ADCs having reduced ENOB and higher distortion at high input frequencies. For this reason, most flash converters must be driven with a wideband op amp which is tolerant to the capacitive load presented by the converter as well as high speed transients developed on the input. Power dissipation is always a big consideration in flash converters, especially at resolutions above 8 bits. primer 8 bit flash ili paralelnij adc 2007 goda ############################# The MAX109, 2.2Gsps, 8-bit, analog-to-digital converter (ADC) enables the accurate digitizing of analog signals with frequencies up to 2.5GHz. Fabricated on an advanced SiGe process, the MAX109 integrates a high-performance track/hold (T/H) amplifier, a quantizer, and a 1:4 demultiplexer on a single monolithic die. The MAX109 also features adjustable offset, full-scale voltage (via REFIN), and sampling instance allowing multiple ADCs to be interleaved in time. The innovative design of the internal T/H amplifier, which has a wide 2.8GHz full-power bandwidth, enables a flat-frequency response through the second Nyquist region. This results in excellent ENOB performance of 6.9 bits. #################################### Iz 8 ostaetsja 6.9 dlja folding interolation National iz 12 bit ostaetsja 8.4 na 1448 mgz http://datasheets.maxim-ic.com/en/ds/MAX109.pdf sowremennij processor SUN/Fujitsu rasseiwaet 58 watt pri 128 gigaflop est kotorie rasseiwajut 100 watt Esli mozno widerzat tochnost komparatorow to sozdat 12 bit flas ADC (potr moschnost 6.8 *16 watt) imeet smisl ? budet dannoe reschenie lutsche chem folding /interpolating ?
milstar: http://china.maxim-ic.com/app-notes/index.mvp/id/810 Understanding flash ADCs Abstract: Flash analog-to-digital converters, also known as parallel ADCs, are the fastest way to convert an analog signal to a digital signal. Flash ADCs are ideal for applications requiring very large bandwidth, but they consume more power than other ADC architectures and are generally limited to 8-bit resolution. This tutorial will discuss flash converters and compare them with other converter types.
milstar: Опытно-конструкторская работа №10 по созданию ультрабыстродействующего модуля аналого-цифрового преобразователя с большим динамическим диапазоном. # Краткая характеристика: Разработка внешнего модуля аналого-цифрового преобразователя DSP160x1-1220 с максимальной частотой дискретизации до 2ГГц и с разрешением АЦП 12 бит. Данный модуль позволит обеспечить мгновенный реальный динамический диапазон SFDR 63-65 дБ (1778 раз) в одновременной частотной полосе до 1000 МГц. Предварительная быстродействующая цифровая обработка сигнала (ЦОС), реализованная на ПЛИС типа XC4VLX160 или XC5V позволит обеспечить входную скорость данных в реальном масштабе времени. Возможность дополнительной обработки сигнала с помощью встроенного сигнального процессора типа TMS320C6415 (опционально). Габариты модуля 190х260х60, принудительная вентиляция, компьютерный интерфейс USB2.0. # Основные задачи решаемые создаваемым оборудованием: * Построение панорамных мониторинговых систем широкополосных сигналов. * Построение радиотехнических систем с ПЧ до 1750 МГц и полосой одновременной обработки до 500 МГц. * Многоканальные измерения и регистрация высокочастотных сигналов. * Регистрация и обработка сигналов в реальном времени в большом динамическом диапазоне. * Регистрация сигнала с высокой скоростью нарастания амплитуды по 1700 каналам. # Экономические показатели: * Срок реализации проекта 11 месяцев * Планируемая рыночная стоимость OEM модуля - 1 299 000 рублей c 18% НДС * Необходимый объем финансирования 19.5 млн. рублей Первые результаты ОКР №10 Появились первые результаты выполнения ОКР №10 разработки и создании ультрабыстродействующего модуля АЦП. Назначение. (Предварительные данные) Внешний модуль быстродействующего АЦП DSP55x1-1220 предназначен для работы с широкополосными сигналами. Уникальное сочетание одновременно широкой обрабатываемой полосы до 1ГГц и высокого разрешения АЦП 12 бит позволяет данному модулю работать в качестве спектроанализатора и осуществлять режим панорамного мониторинга. Отличительные характеристики: * Максимальная частота дискретизации до 2.5 ГГц; * Разрешение АЦП - 12 бит; * SFDR 80 дБ(FS). Предварительные технические параметры: * Входной канал - 1 однополюсный; * Входной амплитудный диапазон ±1В; * Полоса входного сигнала 1 ГГц; * Максимальная частота дискретизации - 2.5 ГГц; http://www.centeradc.ru/stati/web-servisy/shirokopolosnye-priemnye-ustrojstva-svch-s * Разрешение АЦП - 12 бит; * Режим работы памяти: история и предыстория; * Буферная память - 131072 отсчета; * Компьютерный интерфейс - USB2.0 (24МБ/с); * PCI Express x1(200МБ/с), x8 (1.4ГБ/c). Метрологические параметры модуля (в графиках) http://www.centeradc.ru/nir-i-okr/okr-10/
milstar: ГЛАВА 2 ДИСКРЕТНЫЕ СИСТЕМЫ Дискретизация аналоговых сигналов по времени Статические передаточные функции АЦП и ЦАП и погрешности по постоянному току Погрешности по переменному току в тракте преобразователя данных Динамические характеристики ЦАП 1 http://kim-mc.narod.ru/analog_devices/2.pdf ГЛАВА 3 АНАЛОГО-ЦИФРОВЫЕ ПРЕОБРАЗОВАТЕЛИ ДЛЯ ЗАДАЧ ЦИФРОВОЙ ОБРАБОТКИ СИГНАЛОВ АЦП последовательного приближения Сигма-дельта АЦП Параллельные (Flash) АЦП Конвейерные (Pipelined) АЦП АЦП последовательного счета (Bit-Per-Stage) 1 http://kim-mc.narod.ru/analog_devices/3.pdf ГЛАВА 5 БЫСТРОЕ ПРЕОБРАЗОВАНИЕ ФУРЬЕ Дискретное преобразование Фурье Быстрое преобразование Фурье (БПФ) Аппаратное исполнение и тестирование БПФ Требования ЦОС для БПФ приложений в режиме реального времени Эффект расширение спектра сигналов при БПФ и использование взвешивания с функций окна http://kim-mc.narod.ru/analog_devices/5.pdf
milstar: http://www.rfel.com/download/W03007-ISPC_2003_Comparison_of_Wideband_Channelisation_Architectures.pdf wideband chanellisation
milstar: http://www.pentek.com/products/Literature.cfm#TechCast rjad broschjur ,opsianij ... postawschik Naval Research laboratory Brochures - ( top ) * Model 4207 MPC8641D PowerPC & FPGA I/O Processor VME/VXS Board * High-Speed A/D Boards & Real-Time Systems Brochure, Third Edition * Model 4205 VIM/PMC Carrier VME Board Brochure, Second Edition * Elma/Bustronic VXS backplane datasheet * High-Speed VIM I/O Peripherals * Model 4285 Octal 'C40 Processor VME Board Brochure Catalogs - ( top ) * Pentek 2010 Product Catalog * Analog and Digital I/O Product Segment Catalog * Clock and Sync Generator Product Segment Catalog * Radar and SDR I/O Product Segment Catalog * Software and FPGA Tools Product Segment Catalog * Processor Product Segment Catalog * Systems and Recorders Product Segment Catalog
milstar: This is a real-life example of the signal processing involved with a typical monopulse radar application. As shown in Figure 3, the system uses a multi-element antenna where the received signals consist of three types: Azimuth, Elevation and the sum of these two. The signals to be digitized and processed are as follows: Azimuth difference or ΔA which is equal to A1 – A2 Elevation difference or ΔE which is equal to E1 – E2 Sum Channel Σ which is equal to the sum of A1 + A2 + E1 + E2 The phase shift between Σ and ΔE determines the elevation of the target The phase shift between Σ and ΔA determines the azimuth of the target The IF center frequency of these signals is 140 MHz and the IF bandwidth is 40 MHz This signal processing requires three channels of A/D converters Let’s assume that we want to track aircraft targets between a distance of 15 km and 45 km from the radar location. Radar signals travel at the speed of light which is equal to 300,000 km/sec. For targets at 15 km, the round trip for the radar pulse takes 2 x 15 km ÷ 300,000 km/sec = 100 μsec. For targets at 45 km, the round trip takes 2 x 45 ÷ 300,000 km/sec = 300 μsec. Figure 4 shows the timing required to collect the data. Generate a 50 μsec pulse at T0; start collecting data at T = T0 + 100 μsec; stop collecting data at T = T0 + 300 μsec. As shown in Figure 9, we chose the complex baseband signal to have 40 MHz bandwidth. When translated to the 140 MHz IF, the 40 MHz signal extends from 120 MHz to 160 MHz. ######################################## The output sampling frequency must be at least twice the 160 MHz highest frequency, or 320 MHz minimum. Let’s choose 400 MHz to be on the safe side, and use the interpolation filter and DUC to translate the baseband to the IF frequency. Summary The Pentek Model 71621 Transceiver XMC module is a complete radar signal generation, timing and acquisition subsystem. It has the three A/Ds required for monopulse radar and standard on-board support for signal generation and acquisition timing. Radar data acquisition is facilitated by the 200 MHz, 16-bit A/Ds which capture the 140 MHz IF signals with 40 MHz ######################################################################## 140 mgz centr PCH ,40 mgz polosa ot 120 mgz do 160 mgz ----------------------------------------------------------------------- bandwidth. Wideband DDC IP cores convert the IF signals down to baseband. The A/D input controller engine uses a simple parameter table that creates programmable delays, acquisition record lengths and complex acquisition scenarios. Radar waveform generation uses a D/A controller engine with a simple parameter table. It creates multiple waveforms with programmable delays and lengths. The wideband DUC upconverts the digital baseband waveform to 140 MHz IF and the 400 MHz, 16-bit D/A delivers 140 MHz IF signal with 40 MHz bandwidth.
milstar: Radar data acquisition is facilitated by the 200 MHz, 16-bit A/Ds which capture the 140 MHz IF signals with 40 MHz bandwidth. na nastojaschij moment 200 megasample 16 bit imejut ADC --------------- 1.AD9467 250 msps za 120$ /300$ EBZ .Anons 09 2010 http://www.analog.com/static/imported-files/data_sheets/AD9467.pdf?ref=PR_9-27-10_AD9467 http://www.analog.com/en/press-release/9_27_10_ADI_Announces_Industrys_Fatest_16bit_ADC_a/press.html 2.ADS5485 170/200 msps Texas Instruments oktjabr 2009 za 123.70$ http://focus.ti.com/lit/ds/symlink/ads5485.pdf 3. Ochewidno dlja polosi 40 mgz ( minimum 80 megasample) podxodit LTC2209 16 bit 160 megasamples http://cds.linear.com/docs/Datasheet/2209fa.pdf
milstar: In the words of a user, Robert Sgandurra, Senior Product Manager with modular DSP and SDR developer Pentek (www.pentek.com), “TI continues to push the performance envelope with high-speed ADCs. The ADS5485 was a clear choice for our model 7150 Quad A/D Software Radio Module. The higher sample rate means that users will be able to directly digitize nearly 100 MHz of bandwidth, which is invaluable for our customers working on wideband radar and wideband communication systems.” http://mwrf.com/Articles/Index.cfm?Ad=1&ArticleID=20087 ADS5485 An internal dither circuit can be switched on or off as needed to help improve SFDR performance
milstar: http://www.mhprofessional.com/downloads/products/0071485473/SkolnikCh25.pdf Naval research laboratory Digital signal processing
milstar: http://www.emrsdtc.com/conferences/2007/downloads/pdf/conference_papers/A023.pdf powischenie dinamicheskogo diapazona w radarax ... (po zakazu MO Welikobritanii)
milstar: DAnnie po dinamicheskomu diapazonu woennogo radara USA The AN/TPS-75 Radar System [ "Tipsy 75"] is a mobile, tactical radar system capable of providing radar azimuth, range, height, and Identification Friend or Foe (IFF) information for a 240-nautical-mile area. This deployable/transportable radar system is capable of providing long range radar data to support operations and control of tactical aircraft. The TPS-75 today forms the backbone of the US Air Force Air Defense system. The AN/TPS-75 Radar system provides a "real-time" radar airspace picture and data in support of the battle commander and the Ground Theater Air Control System (GTACS) via radio, telephone, microwave relay, or satellite communications link. The AN/TPS-75 radar system includes the UPX-27 IFF/SIF equipment, Tactical Air Operation Interface Gp OA 9194/TYQ-23(V)2, Modular Control Equipment Interface Group (MIG) and AN/TLQ-32 ARM Decoy. The AN/TPS-75 is a mobile ground radar set designed to conduct long-range search and altitude-finding operations simultaneously Weight shelter - app. 8,400 pounds antenna - app. 7,400 pounds Pulse Repetition Frequency (PRF) 235, 250, 275 +/- 0.5 Hz fixed, and two selectable average PRFs; 250 and 275 staggered. For each staggered selection, the transmitter operates sequentially on one of seven PRFs. Transmitter Characteristics peak power - 2.8 MW nominal verage power - 4.7 kW nominal pulse width - 6.8 +/- 0.25 microseconds Receiver Characteristics type -seven logarithmic channels sensitivity - negative 105 dB mds dynamic range - 70 dB search, 70 dB height intermediate frequency - 32 MHz 3-D Coverage (Search, Height and Range) azimuth - 360 degrees (operator controlled blanking optional) elevation angles - 0.5 to 20 degrees above the radar horizon maximum altitude - 95,500 feet range - one to 240 nautical miles scanning rate - approximately 6.5 rpm dimensions 11 feet high by 18 feet 4 inches wide polarization vertical beam width - 1.1 degrees horizontal and 1.55 degrees to 8.1 degrees with a total of 20 degrees (6 stacked beams) ------------ dynamic range - 70 dB search, 70 dB height dinamicheskij diapazon sowremennix 16 bit ADC wische ... ************************************************* + NLEQ /nelinejnij equaliser iz Lincoln laboratory 12-24 db ... http://www.fas.org/man/dod-101/sys/ac/equip/an-tps-75.htm
milstar: Dannie 16 bit ADC k 140 mgz centr PCH ,40 mgz polosa ot 120 mgz do 160 mgz ----------------------------------------------------------------------- ADS5485 TI 200 msps AD9467 250 msps SNR 130 mgz -74.8 db n/d 140 mgz - n/d 74.4/76 db 170 mgz -74.8 db 74.3db/75.8db SFDR 130 mgz -85 db n/d 140 mgz -n/d 94/95 db 170 mgz -78 db 93/92 db SINAD 130 mgz -72.9db n/d 140 mgz n/d 74.4/76 db 170 mgz -71.7 db 74.2db/75.8db Price -125$ AD9467 po dinamicheskomu diapazonu lutsche - dlja primera pentek 92 db + wiigrisch ot NLEQ Lincoln laboratory 12 db = 104 db Xoroscho -------- ----------------------------------------- Summary The Pentek Model 71621 Transceiver XMC module is a complete radar signal generation, timing and acquisition subsystem. It has the three A/Ds required for monopulse radar and standard on-board support for signal generation and acquisition timing. Radar data acquisition is facilitated by the 200 MHz, 16-bit A/Ds which capture the 140 MHz IF signals with 40 MHz ######################################################################## 140 mgz centr PCH ,40 mgz polosa ot 120 mgz do 160 mgz ----------------------------------------------------------------------- bandwidth. Wideband DDC IP cores convert the IF signals down to baseband. The A/D input controller engine uses a simple parameter table that creates programmable delays, acquisition record lengths and complex acquisition scenarios. Radar waveform generation uses a D/A controller engine with a simple parameter table. It creates multiple waveforms with programmable delays and lengths. The wideband DUC upconverts the digital baseband waveform to 140 MHz IF and the 400 MHz, 16-bit D/A delivers 140 MHz IF signal with 40 MHz bandwidth.
milstar: THEORY OF OPERATION The AD9467 architecture consists of an input-buffered pipe-lined ADC that consists of a 3-bit first stage, a 4-bit second stage, followed by four 3-bit stages and a final 3-bit flash. Each stage provides sufficient overlap to correct for flash errors in the preceding stage. The input buffer provides a linear high input impedance (for ease of drive) and reduces the kick-back from the ADC. The buffer is optimized for high linearity, low noise, and low power. The quantized outputs from each stage are combined into a final 16-bit result in the digital correction logic. The pipelined architecture permits the first stage to operate with a new input sample while the remaining stages operate with preceding samples. Sampling occurs on the rising edge of the clock. Each stage of the pipeline, excluding the last, consists of a low resolution flash ADC connected to a switched-capacitor DAC and an interstage residue amplifier (for example, a multiplying digital-to-analog converter (MDAC)). The residue amplifier magnifies the difference between the reconstructed DAC output and the flash input for the next stage in the pipeline. One bit of redundancy is used in each stage to facilitate digital correction of flash errors. The last stage simply consists of a flash ADC. The output staging block aligns the data, corrects errors, and passes the data to the output buffers. http://www.analog.com/static/imported-files/data_sheets/AD9467.pdf?ref=PR_9-27-10_AD9467
milstar: The V-Corp proprietary LinComp approach requires less hardware than phase-plane compensation and provides up to 24 dB or more reduction in harmonic distortion, does not require slope estimates, and is capable of super-Nyquist error compensation (i.e., direct synthesis of high IF data). http://www.v-corp.com/lincomp.htm High-Performance Linearity Error Compensator (LinComp™) Technical Description The high-resolution Linearity Error Compensator (LinComp) is a computationally-efficient digital signal processing method for dramatically reducing harmonic and intermodulation distortion up to 24 dB. The technology is used to predict nonlinear distortion and subtract out the errors. LinComp significantly improves the performance of analog-to-digital converters (ADCs), digital-to-analog converters (DACs), sample-and-hold circuitry, buffer or power amplifiers, or the combination of these devices in an RF chain. This technology improves the dynamic range by up to four bits, enabling very accurate conversion and synthesis of data at high intermediate frequencies (IF) with very high sample rates (e.g., analog-to-digital conversion with > 12-bit dynamic range > 600 MHz IF). This unique technology is only available from V-Corp (U.S. Patent 6,198,416 and numerous patents pending). V-Corp has confirmed the technical efficacy of the LinComp processing methodology via testing with real data from state-of-the-art ADCs, DACs, and power amplifiers. The LinComp processing performs in real-time and can be implemented in FPGA hardware, custom VLSI, a DSP chip, or a software algorithm. Since LinComp is a general linearity compensation method that is easily re-calibrated, systems using LinComp can easily be upgraded to higher performance by incorporating new converter or amplifier technology as it becomes available, thereby maintaining its significant performance advantage. The LinComp technology enables direct sampling or digital synthesis at high IF frequency, which allows very accurate capture or synthesis of wideband data at high frequencies without necessitating the use of gigasample-per-second (GSa/s) sample rates or complex RF mixing electronics. The LinComp technology therefore reduces the size, power, and cost of transceivers by eliminating much of the RF electronics and reducing the digital signal processing requirements (by reducing the data rate from GHz speeds to MHz speeds). Significantly Reduces Distortion in RF Chain (ADCs, DACs, Sampling Circuitry, Amplifiers or Complete RF Chain) LinComp significantly improves the performance of analog-to-digital converters (ADCs), digital-to-analog converters (DACs), sample-and-hold circuitry, buffer amplifiers, and RF power amplifiers (e.g., Solid-State Power Amplifiers (SSPAs) and Traveling Wave Tube High-Power Amplifiers (TWT HPAs) ), or the combination of these devices in an RF signal chain (as shown in Figure 1-1 for a complete RF receiver chain and in Figure 1-2 for a complete RF transmit chain). Linearity errors cause harmonic distortion and intermodulation distortion which can limit the performance of state-of-the-art electronic systems, such as radar systems, digital transceivers for wireless communications, laboratory test equipment, medical imaging, and audio and video compression. Of particular interest is the ability to pre-compensate the transmit signal chain (especially the output power amplifier) to significantly reduce the need to lower the level of the RF power amplification to meet distortion specifications. This reduces the power rating and therefore the size, cost, and power consumption of the output power amplifier in transmitter systems. Reducing errors in digital-to-analog converters, analog-to-digital converters, sample-and-hold circuitry, and buffer and power amplifiers can significantly improve the performance of the critical conversion process.
milstar: Dithering in ADC -powischenie dinamicheskogo diapazona http://www.e2v.com/assets/media/files/documents/broadband-data-converters/doc0869B.pdf
milstar: A 5 Gsps 8-10 bit ADC Platform Concept for RF and Instrumentation Applications François BORE, e2v, avenue de Rochepleine, BP123, 38521 Saint-Egrève Cedex, France www.e2v.com http://www.armms.org/images/conference/5-5_gsps_adc_platform_concept_e2v.pdf There are two ways to increase sampling rate of ADCs: time interleaving of “reasonably fast” ADC or building a faster ADC on a faster process. Each solution have of course drawbacks and advantages, we have developed both solutions for different applications. In this paper we will focus on time interleaving of ADCs, and requirement at ADC level and/or at system level to perform proper time interleaving. We will also see why massive interleaving of “slow” ADC is not such a good idea. Time interleaving of ADCs principle Time interleaving of ADC is a very seductive concept yet its not so obvious to obtain acceptable results, we will see why. The principle is to used m ADC (for practicable reason m is generally a power of 2) to convert the same signal at the same sampling rate fs but with sampling instant shifted of p/m (where p is individual sampling period, that is p=1/fs ), in order to get an equivalent ADC sampling at fseq = m . fs . In a perfect world this would work very well, but unfortunately we are in a real world with many nasty effects such as component matching, noise, phase uncertainty, and even some times different thermal drift. To achieve a correct time interleaved ADC (or TIADC, result of the time interleaving of m ADCs) all these issues must be addressed. First of all we must agree on what is a correct TIADC . A correct TIADC should give result compliant with the system requirement, as would yield a simple fast ADC, if performances are degraded by interleaving they should be recoverable through moderate digital processing overhead (that is no useful information should be lost). What are the requirement for interleaving ? At first order interleaving requires gain matching, offset matching and phase alignment of the interleaved channel. This requirements must be fulfilled over the full frequency range which means that bandwidths of the different channel should also be matched , or that input must be kept well below bandwidth, so that gain are actually matched over the input frequency range. For clarity we will illustrate the cases of 4 interleaved ADCs with a pure sine as input, with ideal response, raw converted signals (1024 point per ADC, and zoom on one input signal period), and reconstructed signals (1 full period, and zoom on critical points). Then we will se impact on these plots and investigate consequences imperfections in the interleaving in each case. Figures hereafter are given with an 8 bit ADC, and an individual over sampling ration close to 2. Source of degradations and proposed solutions: There are two kinds of sources of degradation : 1. deterministic degradation which are easy to compensate in analogue world or to process in digital world , for instance offset, gain, INL or sampling instant misalignment. 2. statistical random degradations: for instance thermal noise in the different signal paths or uncorrelated phase noise for the different sampler. We will first address the deterministic degradation and then we will see how to minimize effect of statistical degradations. Deterministic degradations Offset mismatch errors The first possible imperfection is offset mismatch of the 4 channels, this can be compensated in analogue world thanks to the (digitally controlled) offset tuning of the ADCs or in the digital world in the DSP (which implies slight overhead: adders), to avoid digital overhead it is always preferable to perform this correction in analogue world. If interleaving is done amongst different chips, differences in thermal management of the different chips may requires offset recalibration when system temperature changes. In the case of a 2 or 4 channels interleaving using EV08AQ160, this is not needed thanks to the perfect temperature tracking of the four ADCs on the same chip, and thanks to the flat response over temperature of offset tuning. The effect of offset mismatch errors is independent of the over sampling ratio (OSR), it is the same on any point of the curve. Offset mismatch errors don’t scale with input amplitude. If offset matching errors are close to or larger than one LSB, they are clearly visible on reconstructed signal, otherwise they might be wrongly interpreted as quantization errors. If they are of same order or larger than thermal noise, the SNR of interleaved system will be degraded regarding the SNR of a single core system. Even smaller errors have clear effect on signal spectrum, since they are deterministic and their energy is concentrated in the same frequency slot (clock related spurs at fs or n.fs depending of the error pattern, but independent of input signal amplitude), thus having an impact on SFDR. We can see clearly that offset matching requirement depends on ADC resolution. E2V’s EV08AQ160 includes digitally controlled (through SPI) offset tuning fine enough (that is with of a resolution between one fifth and one tenth of a LSB) so that no further digital processing is needed for offset cancellation. Further more with the EV08AQ160 only one input is used for interleaving of the 4 cores, that is absolute offset error of the external preamplifier or front-end will not have any effect on interleaving process since the same error will be seen by the four ADC cores. Gain mismatch errors The second possible imperfection is gain error mismatch between the different interleaved channels. Once again this can be compensated in the analogue world thanks to the (digitally controlled) gain tuning of the ADCs or in the digital world in the DSP (which implies larger overhead than for offset error cancellation: multipliers), to avoid digital overhead it is always possible to perform this correction in analogue world. If interleaving is done amongst different chips, differences in thermal management of the different chips may requires offset recalibration when system temperature changes. In the case of a 2 or 4 channels interleaving using EV08AQ160, this is not needed thanks to the perfect temperature tracking of the four ADCs on the same chip, and thanks to the flat response over temperature of gain tuning.
milstar: http://lnxcorp.com/Files/dualChannelDRx.pdf DUAL CHANNEL DIGITAL RECEIVER Features Dual Channel Up to 2.2Gsps rate Up to 3.3 GHz Analog 10 bit A/D SFDR - 60dB typ. @ 1.6Gsps SINAD - 47dB typ. @ 1.6Gsps IMD - 60dB typ. @ 1.6Gsps ENOB - 7.5 bits typ. @ 1.6Gsps Sheltered Naval Environment Conduction cooled (standard) 6U VME 64X 3 Virtex IV FPGAs Applications Digital Receiver Electronic warfare Radar Software Radio High Speed Data Acquisition
milstar: powtor s pomoschju NLEQ MIT Lincoln laboratory wiigrisch po dinamicheskomu diapazonu dlja MAX108 8 -bit flash bipoljar -21 db MAX109 8-bit flash SiGe -12 db /1.3 ghz Atmel84sa008 10 bit folding SiGe -13 db/1.5 ghz 60db+13 db = 73 db LTC2209 16 bit konweeernij 160msps dlja polosi 30 mgz(120-150 mgz) +12 db 84/88 db+12 =96/100 db http://www.ll.mit.edu/HPEC/agendas/proc09/Day2/S4_1405_Song_presentation.pdf
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