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Operazionnie ysiliteli ,ZAP/AZP & (ïðîäîëæåíèå)
milstar: 1941: First (vacuum tube) op-amp An op-amp, defined as a general-purpose, DC-coupled, high gain, inverting feedback amplifier, is first found in US Patent 2,401,779 "Summing Amplifier" filed by Karl D. Swartzel Jr. of Bell labs in 1941. This design used three vacuum tubes to achieve a gain of 90dB and operated on voltage rails of ±350V. ###################################################### It had a single inverting input rather than differential inverting and non-inverting inputs, as are common in today's op-amps. Throughout World War II, Swartzel's design proved its value by being liberally used in the M9 artillery director designed at Bell Labs. ######################################################################### This artillery director worked with the SCR584 radar system to achieve extraordinary hit rates (near 90%) that ####################################################################### would not have been possible otherwise.[3] ########################### http://en.wikipedia.org/wiki/Operational_amplifier
milstar: http://rfdesign.com/mag/408rfdf2.pdf The next level of integration in the time-interleaving technology will include four-channel architectures such as the one displayed in Figure 6. These architectures will provide mil/aero system design engineers with 12-bit/800 MSPS and 14-bit/400 MSPS ADC functions using ICs that are commercially available. The development of this architecture will involve the consideration of multiple integration paths. A building block integration approach could offer the three main functions of clock, ADC, and digital post processing as separate modules that form a chip set. This approach provides standard, functional blocks that can be made available for other multichannel ADC system architectures and that offer a simple path for digital upgrades.
milstar: lutschij 16 bit 160 msps ot National http://www.national.com/ds/DC/ADC16DV160.pdf SNR 197 mgz - 76 db SFDR 197 mgz - 89 db
milstar: Waveform Variations by Mode.Although the specific waveform is hard to pre- dict, typical waveform variations can be tabulated based on observed behavior of a number of existing A-S radar systems. Table 5.1 shows the range of parameters that can be observed as a function of radar mode. The parameter ranges listed are PRF, pulse width, duty cycle, pulse compression ratio, independent frequency looks, pulses per coherent processing interval (CPI), transmitted bandwidth, and total pulses in a Time-On-Target (TOT). Obviously, most radars do not contain all of this variation, but modes exist in many fighter aircraft, which represent a good fraction of the parameter range. Most fighter radars are frequency agile since they will be operated in close proximity to similar or identical systems. The frequency usually changes in a carefully controlled, completely coherent manner during a CPI.8 This can be a weakness for certain kinds of jamming since the phase and frequency of the next pulse is predictable. Sometimes to counter- act this weakness, the frequency sequence is pseudorandom from a predetermined set with known autocorrelation properties, for example, Frank, Costas, Viterbi, P codes.16 A major difficulty with complex wideband frequency coding is that the phase shift- ers in a phase scanned array must be changed on an intra- or inter-pulse basis greatly complicating beam steering control and absolute T/R channel phase delay. Another challenge is minimizing power supply phase pulling when PRFs and pulsewidths vary over more than 100:1 range. MFAR systems not only have a wide variation in PRF and pulsewidth but also usually exhibit large instant and total bandwidth. Coupled with the large bandwidth is the requirement for long coherent integration times. This requirement naturally leads to extreme stability master oscillators and ultra low-noise synthesizers.44 http://www.scribd.com/doc/17533868/Chapter-5-Multi-Functional-Radar-Systems-for-Fighter-Aircraft 5.12 MULTIFUNCTIONAL RADAR SYSTEMS FOR FIGHTER AIRCRAFT 1.Real beam map 0.5 -10 mgz 2.Doppler beam sharp 5-25 mgz 3. SAR 10 -500 mgz 4.A-S range 1-50 mgz 5.PVU 1-10 mgz 6.TF/TA 3-15 mgz 7.Sea surface search 0.2 -500 mgz 8.Inverse SAR 5-100 mgz 9. GMTI 0.5-15 mgz 10.Fixed target track 1-50 mgz 11.GMTT 0.5 -15 mgz 12.Sea Surface track 0.2-10 mgz 13.Hi power Jam 1-100 mgz 14.CAl/A.G.C 1-500 mgz 15A-S data link 0.5-250 mgz T.e dlja bolschinstwa funkzij dostatochen AD9467 16 bit ADC 250 msps s Fin do 300 mgz Realnij dinamicheskij diapazon -74 db, ENOB -12 bit 250 msps eto polosa 125 mgz
milstar: Missile defense agency 2008 https://www.dodsbir.net/selections/abs073/mdaabs073.htm ADVANCED SCIENCE & NOVEL TECHNOLOGY 27 Via Porto Grande Rancho Palos Verdes, CA 90275 Phone: PI: Topic#: (408) 564-9236 Dr. Sean P. Woyciehowsky MDA 07-003 Awarded: 02/13/08 Title: High Performance Rad Hard Analog to Digital Converter Architectures Abstract: Electronic components for future space based radar systems on chip (SOC) must function correctly in natural and radiation filled environments while providing state-of-the-art performance. The corresponding SOC must employ advanced, extra low-power, radiation-hardened (RH), analog-to-digital converters (ADCs) capable of operating at multi-giga sampling speeds. To satisfy the described needs, we propose to develop an ADC block with 9 bits of resolution and up to 10Gs/s of sampling speed. The 9 bit wide data will be demultiplexed by a factor of eight to a rate of 1.25Gb/s for direct loading into a following FPGA where signal processing will be performed. Our patent-pending radiation-hardening techniques incorporate a methodology based on protection and redundancy, which provides both total ionization dose (TID) and single-event upset (SEU) tolerance within the IC. The proposed high performance characteristics of the ADC will be achieved by utilizing an advanced SiGe IC fabrication technology. ----------------------------------------------------------------------------- https://www.dodsbir.net/selections/abs073/mdaabs073.htm HITTITE MICROWAVE CORP. 20 Alpha Road Chelmsford, MA 01824 Phone: PI: Topic#: (719) 590-1112 Dr. Michael Hoskins MDA 07-003 Awarded: 02/13/08 Title: High Sample-Rate Ultra-Wideband Track-and-Hold Demultiplexer (2007047) Abstract: Hittite proposes to develop a Radiation-Tolerant Ultra-Wideband Track-and-Hold (T/H) Demultiplexer to address MDA's future needs for microwave signal sampling/data conversion. This development is motivated by the difficulties in achieving high-speed interleaved analog-to-digital converter (ADC) assemblies with good accuracy. ----------------------------------------------------------------------------------------------------------------- A switched-emitter-follower T/H amplifier in the SiGe BiCMOS process with the capability for 15 GHz sampling bandwidth, 6 - 8 Gs/s sample rate, and 8 - 9 bit accuracy will be studied. This high-speed T/H will be used as the front end of a ------------------------------------------------------------------------------------ two-rank T/H sampler/demultiplexer that provides a 2:1 output sample rate reduction, enabling the use of lower rate ADCs in an interleaved assembly without the usual sample timing mismatches that degrade performance. ---------------------------------------------------------------------------------------------------------------------- The T/H demultiplexer can also operate as a subsampler to down convert any Nyquist bands within the 15 GHz bandwidth. This T/H circuit is expected to offer unprecedented bandwidth and operating speed while maintaining accuracy suitable for meeting the X-band and microwave data conversion goals of many military systems. Under Phase I, Hittite will perform a design study with circuit simulations to determine the feasibility and performance of the basic T/H amplifier and the two-rank demultiplexer. Prototype circuits will be built and tested in Phase II. --------------------------------------------------------------------------------------- NU-TREK 17150 Via del CampoSuite 202 San Diego, CA 92127 Phone: PI: Topic#: (909) 864-7858 Mr. William Poland MDA 07-003 Awarded: 02/13/08 Title: Multiplexed, Rad Hard ADC Abstract: The proposed part is a rad-hard, 16-input, 14-bit ADC, with aggregate speed of 200 MSPS. -------------------------------------------------------------------------------------------------------------------- dlj srawnenija 09.2010 National 12 bit 1000 msps ,100 krad The 16 inputs are sampled individually and can be configured as 16 single-ended inputs or 8 differential inputs. The ADC provides 14 data outputs, a data-ready signal, and an over-range indicator. The digital outputs of the ADC are CMOS low-voltage differential signal (LVDS) outputs. The part will be fabricated using Texas Instruments' BiCom3X, a SOI process with CMOS and complementary SiGe bipolar transistors. SiGe bipolar transistors typically have very high total dose hardness, ------------------------------------------------------------------------------------------------------------------------------------------ and we are not aware of an ELDRS problem. The SOI wells prevent latch-up and restrict the silicon volume that can produce photocurrents from either ionizing dose rates or single event strikes. Our designers, Bill Poland, Jim Swonger, Wayne Dietrich and John Branning, have designed over 140 ASICs, many of them rad-hard. They worked together on a 14-bit rad-hard ADC, on which the proposed part is based. Nu-Trek is an emerging suppler of rad-hard parts, with four parts coming on sale in 2008. The Nu-Det has already been inserted into the MKV and NGIMU. The Clam/NED is slated for insertion in the Army's FCS.
milstar: A Wide Dynamic Range Radar Digitizer http://highfrequencyelectronics.com/Archives/Sep08/HFE0908_S_Crean.pdf However, converting from the analog to digital domain introduces errors which limit overall system performance. One of the most important limitations is dynamic range, which is the range of signal amplitudes that can be captured by an ADC. This defines the minimum detectable signal ##################################### in the presence of a larger, interfering signal. ############################## otrazennij signal ot celi w prisutstwii pomex This is set both by the number of bits and the Signal to Noise Ratio(SNR). ############################################ A 16-bit ADC is used to capture the (C Band) transmit pulse after down conversion to IF. This adequately records the start pulse for synchronization and associated signal phase for demodulation. However, the input RF return signal has a dynamic range of 105 dB, which is greater than the (ideal theoretical) dynamic range for any commercial, high-speed ADC (limited to 16 bits). This dynamic range requires a 20-bit ADC as shown. To provide this capability, the normal input signal range is extended using instantaneous automatic gain control (AGC) as part of the digital signal processing (DSP) function. ADC Dynamic Range An ideal ADC has an SNR equal to 6.02 × N + 1.76 dB, where N is equal to the number of bits. For a 16-bit converter, this translates to 98 dB, which is the maximum (ideal theoretical) limit for input signal dynamic range. However, for high speed converters this ideal SNR is never achieved due to other issues which conspire to limit the SNR to a much lower value. These issues include ADC nonlinearity, front end amplifier noise and sample clock jitter. A typical SNR value for a high-speed (120 MHz sample rate) ADC is about 76 dB, which is well below the theoretical limit. sent 2010 -AD9467 -73-74 db na 300 mgz ,250 msps ##################################### Wide Dynamic Range Digitizing As mentioned previously, recording weather radar signals requires a minimum of 105 dB of dynamic range. Since the dynamic range of available high speed ADCs is limited to 90 dB (with processing gain), with further reductions down to 80 dB due to the clock source (jitter), a simple ADC is not sufficient. Symtx Inc. has implemented a dual ADC scheme to increase digitizer dynamic range as shown in Figure 3. The design uses a high-gain channel to process low-level signals and a low-gain channel to process high-level signals, with simultaneous sampling of both channels in parallel. The gain difference between the high-level and low level ADCs is compensated with an appropriate n-bit left shift to give the correct scaling. A DSP after the two ADCs then selects the correct ADC output, adjusts for gain, and merges the two to create a 20-bit word with the desired dynamic range. The process is essentially an instantaneous AGC which responds to the signal amplitude at the input. Since range bins for weather radars are on the order of 1 microsecond, the DSP operates by scanning the data for each range bin to determine the maximum signal amplitude. If this is within the maximum level for the high-gain (low-signallevel) ADC, it is used for data collection (to maximize signal resolution). If any sample exceeds this threshold, all data in the range bin is collected using the low-gain (high-signallevel) ADC. Summary High-speed RF signal capture with wide dynamic range signals is readily achievable with today's high-speed ADCs. With careful design followed by the appropriate digital signal processing, it is possible to capture and recreate signals with dynamic ranges in excess of 100 dB.
milstar: However, as discussed in the article entitled “A Wide Dynamic Range Radar Digitizer,” [1] converting to the digital domain introduces errors which limit overall system performance. One of the most important limitations is dynamic range, which is the range of signal amplitudes that can be captured by an ADC. This is determined by the number of conversion bits as well as by the signal-to-noise ratio (SNR) of the analog components (amplifiers, mixers, etc.) which precede the ADC. http://highfrequencyelectronics.com/Archives/Nov08/1108_Friedman.pdf is the ability to accommodate a dynamic range of at least 105 dB between the maximum- capable and minimum-detectable amplitudes that may occur in the course of a single radar trace. The actual system operates above 5 GHz and includes RF mixers, filters, amplifiers, tunable frequency sources, and other analog devices that are not shown in the figure. However, the dynamic range and SNR are set primarily by the IF devices in this diagram The receiver in the radar itself as originally designed used analog AGC to compress the signal amplitude range prior to digitization. However, this was found to cause distortion and other undesirable effects. The AGC was later eliminated by converting to an all-digital receiver using an arrangement of two 14-bit ADCs with a 24-dB gain offset. One or the other ADC output is used according to the instantaneous amplitude of the signal, and the resulting digital value is bit-shifted as needed to compensate for the gain offset, resulting in an effective 20-bit ADC. Note that this does not provide 20 bits of resolution, since only 14 bits are used for any given sample, but the ratio of maximum-to-minimum signal level is equivalent to that of a 20-bit ADC. Dynamic Range For purposes of this discussion, consider the dynamic range to be the ratio of maximum-capable to minimumdetectable signal amplitude. In terms of the DAC alone, the minimum-detectable signal is determined by its quantization. For example, the dynamic range requirement of 105 dB corresponds to a ratio of approximately 217.5 or a shift of 17.5 bits. This can be shown to be accommodated by the 20-bit word as follows. Allowing for a sign bit leaves 19 bits for the peak magnitude of the largest signal. Shifting right by 17.5 bits leaves 1.5 bits for the peak of the smallest signal, or 1 bit for the RMS level, i.e., the RMS of the smallest signal is equal to the smallest value that can be represented (the magnitude difference corresponding to the low-order bit). More generally, the dynamic range is determined by the SNR, defined as the ratio of the maximum signal amplitude to the noise floor when a small signal is present (so as to bring quantization noise into account). Assuming a signal must be above the noise floor by a certain amount (in dB) in order to be detectable, the dynamic range will be equal to the SNR less this amount. The noise present at the DAC output consists of quiescent (mostly thermal) circuit noise, which is fixed in absolute level, plus quantization noise and other noise generated in the DAC (as specified by the SNR given in the data sheet), both of which are relative to the DAC’s full-scale output value. For a full-scale sinusoidal signal, the SNR defined by quantization noise alone is 6.02 × N + 1.76 dB, where N is the number of bits, giving approximately 98 dB for a 16-bit DAC, or 122 dB for 20 bits. This sets an upper limit on the data-sheet SNR, which takes all internal noise sources into account, including nonlinear intermodulation effects which generally will depend on the actual composition of the signal. For the purposes of this article, we assume that the DAC output level is scaled so that the DAC-internal noise (including quantization noise) is above the quiescent (thermal) noise, so that the dynamic range is determined essentially by the DAC noise. If this is not the case, then the dynamic range is reduced by the amount by which the DAC noise falls below the quiescent noise.
milstar: http://www.naic.edu/ http://en.wikipedia.org/wiki/Arecibo_Observatory The World's Largest and most Sensitive Radiotelescope located in Arecibo, Puerto Rico The observatory's 305 m (1,001 ft) radio telescope is the largest single-aperture telescope (cf. multiple aperture telescope) ever constructed. It carries out three major areas of research: radio astronomy, aeronomy (using both the 305 m telescope and the observatory's lidar facility), and radar astronomy observations of solar system objects http://www.naic.edu/~nolan/radar/ri.html The radar data acquisition system has three primary modes of operation for planetary radar: hardware decoding of a coded signal, direct sampling of a coded signal, and CW spectrometry The initial input for this system is a 260 MHz IF (left and right circular down-converted from 2380 MHz upstairs). Because of our narrow-band signal, conversion to circular in the turnstile upstairs probably gives us cleaner polarizations than using the downstairs IF/LO. This signal has not been Doppler corrected. This signal comes down on an optical fiber, then out of the downstairs IF/LO system on the .2-.4 GHz channel. The analog gain is set in the IF/LO, with a fine gain control later in the signal path. There are two independent (polarization) channels in this hardware, but there is only one set of frequency synthesizers. The 260 MHz signal is passed through a many-pole 20 MHz analog bandpass filter. This filtered 260 MHz signal is then down-converted to baseband by a Doppler-correcting mixer, then analog low-pass filtered for sideband rejection. The signal power is measured at this point for setting the gains to get good dynamic range into the digitizers. Decoder At this point, the signal is fed to an 8-bit digitizer running at 80 MHz. The digitizer feeds the software-selectable digital sinc filters, which provide separate 9-bit I and Q outputs. The filters provides 4-bit input to the hardware decoder. Which 4 bits is software selectable.
milstar: ADC interleaving ,array ... powischenie skorosti ,no ostalnie parametri yxudshajutsja ************************************************************************* http://www.national.com/ds/DC/ADC12D1800.pdf daze esli 2 ADC na odnom kristalle ---------------------------------------------- primer sentjabrskij 2010 ADC12D1800 National Semiconductor ,12 bit 3.6 gsps 1.Non des mode - kazdij ADC otdelno so skorostju 1.8 gigasample 2 Des mode -sdwoennij so skorostju 3.6 gigasampel ENOB 8.4 bit (non des ) 8 bit (des) Fin 1448 mgz SINAD 52.5 db (non des) 49.8 db (des) SNR 53.1 db(non des) 50.1db(des) SFDR 60.3 db(non des) 55.6 db(des)
milstar: For example, in military radar systems, a single ADC12D1X00 combined with a digital down-converter can replace multiple mixers, filters, amplifiers and local oscillator stages used in traditional heterodyne double- or triple-conversion radio implementations. ##################### Since this new class of SDRs requires the ADC to sample wide-bandwidth signals, a new set of metrics such as noise-floor, NPR and IMD provide the best measure of a system's capability to extract narrowband information from a wideband spectrum. This is in stark contrast to traditional ADC specifications -- signal-to-noise ratio (SNR), spurious-free dynamic range (SFDR), and effective number of bits (ENOB) -- which focus on single-tone performance in the Nyquist bandwidth and do not provide the best gauge of a system's overall capability. ...and IMD ########### Dlja ADC!2D1800 DESIQ mode -61 db 1212 mgz ,1217 mgz -54 db chut lutsche chem SINAD na 1448 mgz -50db ------------------------------------------------------
milstar: Menee skorostnoj 12D1000 non des -mode ,1000 megasample -sootw .mozet obrabotat 500 mgz polosu signala protiv 12D1600 non des mode - 800 mgz , 12D1800 non des mode ,1800 megasample ,900 mgz ENOB 8.6 db 8.6 db 8.4 db 1448 mgz SINAD 53.6 db 53.8 db 52.5 db SNR 54.1 db 55 db 53.1 db SFDR 67 db 61.9 db 60.3 db http://www.national.com/ds/DC/ADC12D1000.pdf VErsija ,stojkaja k radiazii tolko 12D1000 na 1000 megasample
milstar: srawnenija ADS5400 TI 1000 megasample(cena 775 $) s NS 12D1000 1000 megasamle ENOB ADS5400 12D1000 498 mgz n/d 9.4 db 600 mgz 9.37 db n/d 850 mgz 9.3 db n/d 998 mgz n/d 8.9 db SINAD 498 mgz n/d 58.2 db 600 mgz 58.2 db n/d 850 mgz 57.8 db n/d 998 mgz n/d 55,4 db 1200 mgz 57.5 db n/d 1448 mgz n/d 53.6 db 1700 mgz 54.2 db n/d SFDR 498 mgz n/d 68.7 db 600 mgz 72 db n/d 850 mgz 71 db n/d 998 mgz n/d 66 db 1200 mgz 66 db n/d 1448 mgz n/d 67 db 1700 mgz 56 db n/d http://focus.ti.com/lit/ds/symlink/ads5400.pdf http://www.national.com/ds/DC/ADC12D1000.pdf
milstar: http://www.atmel.com/dyn/resources/prod_documents/doc5431S.pdf atmel 10 bit / 2.2 gsps 2003 goda SiGE ,1100 $ w 2005 godu na 1000 mgz 7.8 bit ENOB Applications • Direct RF Down Conversion • Ultra Wide Band Satellite Receivers • Radars and Countermeasures • High-speed Acquisition Systems • High Energy Physics • Automatic Test Equipment potr .moschnost 6.8 watt http://www.bdtic.com/ATMEL/Broadband/index.html Releases Atmel Breaks the 2GHz Barrier for High-speed Digitization With a Linear 10-bit 2.2 Gsps Analog-to-Digital Converter First ADC Delivering 2.2 GHz Sampling Rate 50 Percent Faster than Competitors Products Grenoble, France – June 7, 2005. . Atmel® Corporation (Nasdaq: ATML), a global leader in the development and fabrication of advanced semiconductor solutions, announced today the industry's fastest commercially available 10bit analog-to-digital converter (ADC) with a clock frequency of 2.2 Gsps, providing high performance over 1st and 2nd Nyquist zones. The new AT84AS008GL is fully pin-compatible with Atmel's TS83102G0BGL 10-bit 2 Gsps ADC, allowing for seamless upgrades and providing a full 8 Effective Number of Bits at 1.7 Gsps in 1st Nyquist for high speed digitization applications such as broadband test & measurement equipment, high speed data acquisition, telecommunications and defense. The AT84AS008GL is the latest in Atmel's family of Gigahertz 10-bit data converters, providing a new level of linear performance over 1st and 2nd Nyquist zones while reducing power consumption and improving frequency spectral response. By leveraging Atmel's expertise in fast ADC design and incorporating the latest advances in the company's folding and interpolating architectures, the new device provides excellent dynamic performance of 55dB SFDR and 51dB SNR at 2.2 Gsps in first Nyquist conditions. Furthermore, the 3.3 GHz input bandwidth extends ADC operation well into the 2nd Nyquist zone with essentially flat performance: SNR remains at 48 dB and SFDR at 55 dB. Interfacing the AT84AS008GL with FPGAs, DSPs, or ASICs is possible through a new Atmel companion DMUX chip, AT84CS001TP. It provides 10-bit 2.2 GHz performance with 1:4 or 1:2 LVDS compatible demultiplexing ratios. "The AT84AS008GL is a clear winner over any other high-speed ADC on the market," said Andrew Benn, marketing manager for Atmel's Broadband Data Conversion product line. "This ADC reaffirms our commitment to providing fast linear data converters as an enabling technology for next generation digitization applications. It sets a new standard for digitization speed and accuracy and allows system designers to reach new levels of performance." The AT84AS008GL is a step-ahead of the competition, being the first ADC available on the market to provide a guaranteed 2.2 GHz sampling rate, nearly 50 percent faster than the closest competitor. In addition, the FFT spectral response remains very stable over temperature and clock frequency variations, allowing significant system performance enhancement through digital processing even under severe environmental conditions. The AT84AS008GL is delivered in a CBGA 152 ceramic package and operates over Commercial and Industrial temperature ranges. A Military grade version is planned for availability in 2006. Samples are available now with production quantities in July 2005, at a unit price of $1100 for a 1K-piece quantity. About Atmel Atmel is a worldwide leader in the design and manufacture of microcontrollers, advanced logic, mixed-signal, nonvolatile memory and radio frequency (RF) components. Leveraging one of the industry's broadest intellectual property (IP) technology portfolios, Atmel is able to provide the electronics industry with complete system solutions. Focused on consumer, industrial, security, communications, computing and automotive markets, Atmel ICs can be found Everywhere You Are®. ©Atmel Corporation 2005. All rights reserved. Atmel®, logo and combinations thereof, Everywhere You Are® and others, are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. Information Further information on the AT84AS008GL can be found at: http://www.atmel.com/dyn/products/product_card.asp?part_id=3679 For more information on Atmel's Broadband Data Conversion products go to: http://www.atmel.com/products/Broadband/overview.asp Press Contact Sylvie Mattei, Communications Manager – Atmel Grenoble Tel: +33 4 76 58 30 25, Email: sylvie.mattei@gfo.atmel.com Veronique Sablereau, Corporate Communications Manager - Europe Tel: +33 1 30 60 70 68, Fax: +49 71 31 67 24 23 Email: veronique.sablereau@atmel.com Ford Kanzler, Manager of Corporate Press Relations - USA and Asia Tel: +1 408 436 4343, Email: pr@atmel.com
milstar: Analog–to–Digital Converter Technology and Corresponding Signal Processor Throughput and Dynamic Range. For the PATRIOT radar, advanced signal process technology is required to support dynamic ranges while maintaining the throughput, size, weight, and prime power requirements. Applicable advanced signal processing techniques, such as maximum entropy method (MEM), are required for incorporation into PATRIOT, along with a concept for their utilization, signal processor hardware concepts, and an assessment of their performance improvement over pulse Doppler for various environments. The PAC–3 radar signal processors currently use 12–bit A/D converters for narrow band actions. For radar performance in clutter, more dynamic range is needed—up to 14–16 bits for wide band. system/transmitter intermediate frequency (S/T–IF) receiver subsystem changes would require the incorporation of 16 bit A/D converters into the PATRIOT S/T–IF receive subsystem, along with the incorporation of the advanced signal processor hardware and processor resident software. Included in the proposed architecture and design is the removal or disabling of the current digital signal processor and the replacement of their functions in the advanced signal processor. The CDI–3 receiver subsystem was designed for later incorporation of 12 bit A/D converters when available. The incorporation of the 14–bit converter will require some redesign of the receiver. The value added for PATRIOT is improved fire unit search, track, and CDI capabilities in low altitude, high clutter or extensive antitactical missile debris environments. The technology infusion period is from 1QFY02 to 4QFY03. [POC: Rodney Sams, PATRIOT, (205) 955–3166] http://www.fas.org/man/dod-101/army/docs/astmp98/de.htm , more dynamic range is needed—up to 14–16 bits for wide band Gde ix wzjat ... Lider 16 bit AD9467 250 megasamples ,Fin 300 mgz ------------------------------------------------------------------------------------------ 250 megasamples eto wsego 125 mgz Dlja X band (8-10 ghz) polosa 1000 mgz /razreschenie 250 mm --------------------------------------------------------------------------- prodwizenie texnologii 1.5 bita za 8 let
milstar: ADS5463 toze 12 bit kak i ADS5400 no 500 msps wmesto 1000 msps Hirel -wiskoja nadeznost ,class V 5463 -7500 $ za stuku w partijax p o100 stuk 5400 -775 $ http://focus.ti.com/lit/ds/symlink/ads5463-sp.pdf
milstar: Hall: We did engage with one company by the name of Mercury Computer Systems. ----------------------------------------------------------------------------------------------- postawschik Northrop They build data acquisition cards and essentially the company's creates data acquisition card solutions. The company is focused on military/aerospace applications. What results is a proof of concept through these data acquisition cards and then the company will typically do a custom job for a particular project. Brian Kimball, Principal HW Engineer at Mercury Computer Systems told us: “We needed a 16-bit, 250-MSPS data converter with 90 db of SFDR for one of our key customer's highly advanced, data acquisition systems. The AD9467 data converter was designed into this customer's system because it met our SFDR, ENOB, and power requirements. Analog Devices worked with us as trusted advisors to provide early-access silicon and design support to enable the timely development of our prototype product.” What caught MCS' customer's attention was their system's performance based on our ADC. We've been working with Mercury for a couple of quarters now in terms of early engagement and early samples for them. It has been very successful for them. http://www.analog.com/static/imported-files/data_sheets/AD9467.pdf?ref=PR_9-27-10_AD9467
milstar: http://www.tekmicro.com/PDFs/QuiXilicaV5wp.041508.pdf QuiXilica V5 Architecture: The High Performance Sensor I/O Processing Solution for the Latest Generation and Beyond Andrew Reddig President, CTO TEK Microsystems, Inc. Military sensor data processing applications for communications, radar, and electronic warfare have an insatiable demand for increased signal performance. Sensors continually require more channels, increased processing capabilities, higher memory performance and greater communications bandwidth. Advanced applications in Radar, EW, ELINT, SIGINT and Telecom require the performance offered by the very latest component technologies of FPGAs, memories, communications standards, etc. To get the best out of these latest technologies, Tekmicro’s new QuiXilica V5 Architecture encompasses a holistic architectural philosophy resulting in an advanced family of products that serves the needs of demanding sensor I/O applications. The QuiXilica V5 Architecture builds upon the success of the current QuiXilica board family, utilizing Xilinx Virtex-5 FPGAs, DDR3 SDRAM and the latest enhancements in flexible I/O communication modules (SFP+ and QSFP). These components are carefully interconnected and balanced into an architecture optimized for target applications in sensor I/O processing. QuiXilica V5 Architecture The QuiXilica V5 Architecture is the basis for a variety of digitizer boards in multiple form factors. A very broad range of analog sensor I/O configurations provide easy compatibility with the widest range of analog signal options, addressing multi-channel, high resolution sampled data requirements at 4 Gsps (Gigasamples per second) and beyond. QuiXilica V5 boards are designed to retain the strong underlying principles and core feature set of the previous generation of QuiXilica digitizers such as high speed front panel I/O, high signal integrity, high bandwidth memory, and significant FPGA resources. Building upon the success of the current QuiXilica board family and retaining a migration path for current users, the analog configuration options that are planned to be available for QuiXilicaV5 digitizers are: 6 x 16 bit 160MSPS ADC & 1 x DAC channel 7 x 16 bit 500 MHz DAC channels 2 x 10 bit 2.2 GHz ADC channels 2x 12 bit 2.2 GHz DAC channels 1x 10 bit 2.2 GHz ADC channels with 1x 12 bit 2.2 GHz DAC channels 6 x 12 bit 500MHz ADC channels 2 x 8 bit 4GHz ADCs channels + further configurations to be determined The efficiency of the QuiXilica V5 Architecture is best observed in the context of classical sensor I/O data processing applications. These applications generally consist of a number of sensor inputs, such as ADCs, which produce a set of digitized data streams followed by a number of processing stages. Multiple sensors may be utilized to digitize data from receivers spread in physical distance or to achieve processing gain through channel combining. Each stage of processing typically aims to reduce the data rate through signal processing until a manageable low rate data stream can be provided to the user for analysis. This process, shown in Figure 4 can be conceptualized as a funnel with a large number of sensors providing input data streams that are gradually reduced using a number of processing stages. At the bottom of the funnel, processed data is output after having been processed and combined to a manageable rate. This signal processing architecture is typical for beamformers and front-end sensors used in SIGINT and ELINT applications.
milstar: http://www.tekmicro.com/products/digitizers.cfm Overview: TEK Microsystems, Inc., was founded in 1981 and is headquartered in Chelmsford, Massachusetts. Key customers include defense contractors such as Raytheon, Northrop Grumman, Lockheed Martin, General Dynamics, Thales, BAE, and several government research organizations in the U.S. and abroad. TEK Microsystems, Inc. designs, manufactures and markets a wide range of advanced high-performance FPGA based sensor I/O processing products for embedded real-time computing systems. The comprehensive product line includes advanced ADC/DAC interfaces, complete data acquisition and data recording/storage systems, digital I/O XMC/PMC modules as well as advanced signal processing systems. These products are used in real-time systems designed for data acquisition, instrumentation, control systems and signal processing in customer applications such as reconnaissance, signals intelligence, satellite telemetry, mine detection, medical imaging, radar, sonar, semiconductor inspection and seismic research. ########################################################## Dual 10-bit ADC Proteus-V5 VXS – 5 GSPS per Channel Arlington, VA – May 11, 2010 – At the IEEE Radar 2010 conference, TEK Microsystems, Incorporated, the leading supplier of VME and VXS-based signal acquisition, generation and FPGA-based processing products, has announced the latest member of our QuiXilica product family, the Proteus-V5. The new Proteus-V5 features two 10-bit analog-to-digital converter (ADC) channels, each operating at up to 5.0 GSPS (Gigasamples per second). Like all members of the QuiXilica-V5 VXS family, the Proteus-V5 is compatible with legacy VME systems as well as newer ANSI/VITA 41 VXS based systems and combines high density FPGA processing with the ultimate in ultra wide band ADC signal acquisition. Proteus-V5 ADC Supports Ultra Wide Band Signal Acquisition Proteus-V5 is based on the e2v EV10AQ190 ADC device, which contains four separate 10-bit 1.25 GSPS A/D converters. Each device can be configured to operate as four 1.25 GSPS converters in a non-interleaved mode, or as either 2 channels at 2.5 GSPS or 1 channel at 5 GSPS using the converters in an interleaved mode. In all modes, the converters provide 10-bit resolution and input bandwidth exceeding 3 GHz. This allows the ADC to be used as a 5 GSPS converter for 1st Nyquist applications or as a high density multichannel ADC for lower bandwidth applications using either 1st or 2nd Nyquist sampling. ############################################## Two or Six Channel 12-bit ADC with Up To 3.2 GSPS per Channel Arlington, VA – May 13, 2010 – At the IEEE Radar 2010 conference, TEK Microsystems, Incorporated, the leading supplier of VME and VXS-based signal acquisition, generation and FPGA-based processing products, has announced the latest member of our QuiXilica product family, the Calypso-V5. The new Calypso-V5 supports either two 12-bit analog-to-digital converter (ADC) channels at 3.2 GSPS (Gigasamples per second) or six channels at 1.6 GSPS. Like all members of the QuiXilica-V5 VXS family, the Calypso-V5 is compatible with legacy VME systems as well as newer ANSI/VITA 41 VXS based systems and combines high density FPGA processing with the ultimate in ultra wide band ADC signal acquisition. “Tekmicro is committed to providing our customers with the best available ADC technology for 10, 12, and 16 bit resolutions. The new Calypso-V5 is another industry first for Tekmicro, providing the fastest available sampling rate for 12-bit signal acquisition”, comments Andrew Reddig, CEO / CTO of Tekmicro. “By using National Semiconductor’s latest ADC device, we are able to meet our customers’ requests for multi-channel signal acquisition and processing using 2nd Nyquist sampling and 500+ MHz staring bandwidth, which addresses a critical “sweet spot” for certain applications sampled at 1.333 GSPS”. Calypso-V5 ADC Supports Ultra Wide Band Signal Acquisition Calypso-V5 is based on the latest National Semiconductor ADC device which supports either a pair of channels in non-interleaved mode or a single channel using 2:1 interleaved sampling. Calypso-V5 contains four ADC devices, supporting a total of either six channels plus trigger at 1.6 GSPS or two channels plus trigger at 3.2 GSPS. In all modes, the converters provide 12-bit resolution and open analog bandwidth exceeding 2 GHz. This allows Calypso-V5 to be used as a 3.2 GSPS converter for 1st Nyquist applications or as a high density multichannel building block for lower bandwidth applications using either 1st or 2nd Nyquist sampling. Calypso-V5 also includes sample-accurate trigger synchronization in all modes, allowing coherent processing of multiple input channels both within a single card and across multiple cards. This allows applications of up to 108 channels to be supported within a single chassis
milstar: Tekmicro Supplies Signal Processing System for NASA Glenn Research Center New Texas Instruments ADS5400 Supports Tekmicro’s Unprecedented Performance ###################################################### on stoit 775 $ w partijax po 100 stuk ,12 bit 1000 megasamles -------------------------------------------------------------------------- Chelmsford, MA – October 26, 2009 – TEK Microsystems, Inc. announced it has shipped follow up system orders to NASA Glenn Research Center in Cleveland, OH. Glenn is developing a VXS-based satellite communications test set for ground based validation of satellite equipment. The test set will be used ################################################################ for the Tracking and Data Relay Satellite System compatibility testing as part of NASA’s Constellation Program. Successful development will result in additional orders of totaling over $1M. NASA’s Constellation Program is building the next generation of space vehicles that will take astronauts to low Earth orbit, the moon, and eventually to Mars. Tekmicro’s Titan-V5 VXS and Callisto VXS boards are now being used in the program. Titan-V5 VXS was selected because of its first-in-the-industry levels of high performance, low latency, and signal integrity. The Titan-V5 combines four channels of 1 GSPS 12-bit ADCs, four channels of 1.2 GSPS 14-bit DACs and three Virtex-5 FPGAs to provide the highest bandwidth channel count per slot available for VXS products on the market today. By providing a massive FPGA processing resource at the heart of the VXS communications fabric, Callisto achieves an optimal balance between processing power and IO bandwidth; maximizing the value that can be extracted from the use of FPGAs for signal processing. “The Titan-V5 utilizes best-in-class devices for digitization and signal generation, and, it redefines low latency by providing almost instantaneous acquisition-to-response times when compared with older architectures using multiple boards or modules,” comments Andy Reddig, CEO/CTO of Tekmicro. “Our ability to implement the newly announced ADS5400 from Texas Instruments gave our engineering team technology with nearly 2x the speed of competitive offerings. The culmination of these advanced technologies gives Titan-V5 a competitive edge for signal processing solutions.” In addition to Callisto and Titan-V5, Tekmicro offers the broadest range of Xilinx Virtex-5 based streaming I/O and FPGA processing solutions for both analog and digital I/O in the industry today in both commercial and rugged options. About TEK Microsystems, Incorporated Founded in 1981 and headquartered in Chelmsford, Massachusetts, Tekmicro designs, manufactures and delivers a wide range of advanced high-performance boards and systems for embedded real-time data acquisition, data conversion, storage and recording. Tekmicro provides both commercial and rugged grade products that are used in real-time systems designed for a wide range of defense, intelligence and industrial applications such as C4ISR, SIGINT, EW and Radar.
milstar: Tarvos-V5 Overview Designed to meet the needs of demanding sensor-processing applications across a range of environments, the Tarvos-V5 employs three Xilinx Virtex®-5 FPGAs, advanced DDR3 SDRAM, and the highest resolution digital-to-analog and analog-to-digital converter technologies available at a 185 Msps sampling rate. Each analog input channel uses a Linear Technology LTC2209 16-bit A/D converter, which is designed for digitizing high frequency, wide dynamic range signals within an analogue input bandwidth of 700 MHz. A range of options are available for input signal conditioning to support different receiver applications. http://www.tekmicro.com/news_events/TarvosV5.cfm http://cds.linear.com/docs/Datasheet/2209fa.pdf
milstar: http://www.lnxcorp.com/Files/Drx_RX00103-008.pdf Dual Channel Wideband Digital Receiver RX00103-008 Features • Dual Channel, wideband data acquisition and real-time signal processing module • 2.2 Gsa/sec, 10-bit analog-digital converter • > 55 dB SFDR • 7.6 Effective Bits @ FS = 1.4 Gsps, FIN = 700 MHz • Real-time DSP using Xilinx Virtex-4 series Field Programmable Gate Arrays • VME, HotlinkTM, and RS232 interfaces • Rugged, conduction cooled design. • For use in applications such as EW, ESM, Radar and software defined receivers • Offered with or without wideband downconverter The board includes two AT84AS008 A/Ds from Atmel which have a maximum sample rate of 2.2 Gsa/sec at 10-bits with a 3 GHz full power input bandwidth. Spurious free dynamic range is 55 dBc (7.4 effective bits at FS = 1.4 Gsa/sec, fIN = 700 MHz). The A/D's sampling delay and gain can be adjusted to support synchronizing and interleaving multiple A/D channels.
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