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Operazionnie ysiliteli ,ZAP/AZP & (продолжение)
milstar: 1941: First (vacuum tube) op-amp An op-amp, defined as a general-purpose, DC-coupled, high gain, inverting feedback amplifier, is first found in US Patent 2,401,779 "Summing Amplifier" filed by Karl D. Swartzel Jr. of Bell labs in 1941. This design used three vacuum tubes to achieve a gain of 90dB and operated on voltage rails of ±350V. ###################################################### It had a single inverting input rather than differential inverting and non-inverting inputs, as are common in today's op-amps. Throughout World War II, Swartzel's design proved its value by being liberally used in the M9 artillery director designed at Bell Labs. ######################################################################### This artillery director worked with the SCR584 radar system to achieve extraordinary hit rates (near 90%) that ####################################################################### would not have been possible otherwise.[3] ########################### http://en.wikipedia.org/wiki/Operational_amplifier
milstar: Sowetskie AZP i ZAP http://offtop.ru/dustyattic/v1_702988_all_.php?of13639=1gv21b15gos0bjk6tn5nkl95i1 Ne nado smejatsja ... W 35 ghz MMW radar Lincoln laboratory s 13.7 metr aantennoj i polosoj signala 1000 mhz(potom 2000 mhz) w nachale 90 posle mnogokratnix preobre. chastoti ispolzowalsja strech processing s 10 bit 20 msps AZP w üpolose 2.5 mhz-7.5 mhz Sowetskie AZP imeli te ze dannie ( pri nizkom wixode godnix) koipja s linka Уважаемый, Carbon, хотел бы внести небольшое уточнение. Приведенный Вами на фото АЦП 1107ПВ3Б из "Венты" имел частоту преобразования 50МГц, а вот 1107ПВ3А имел уже 100МГц. С такой же частотой 100МГц 1107ПВ4 (Тема "Веда") имел разрядность 8. И уже на излете советской власти (как писал уважаемый Georg)появился лучший советский АЦП 1107ПВ6 - 10р 15 МГц.
milstar: http://ns1.elcp.ru/developer-r/news/company/2113/doc/45882/ Разработаны отечественные 14-разрядные 20 МГц АЦП В ГУП НПЦ «Элвис» разработаны отечественные микросхемы двухканального аналого-цифрового контроллера ввода сигналов 9008ВГ1Я. Приборы могут быть использованы в качестве обычного двухканального АЦП, а также для замены AD9225, AD9240, ADS850 (Analog Devices), LTC2246, LTC2226 (Linear Technology). Микросхемы выполнены в виде многокристального модуля и содержат два кристалла 14-разрядных АЦП конвейерного типа с частотой оцифровки до 20 МГц и цифровой контроллер. Кристаллы изготовлены по 0,25 мкм технологии и размещены в 192-выводном корпусе BGA размером 17х17 мм. Диапазон рабочих температур от -60 до 85°C. 9008ВГ1Я оцифровывает внешние сигналы/изображения, хранит их в буферной памяти типа FIFO и выводит информационный поток через интерфейс подключения к порту памяти (MPORT) процессоров серии «Мультикор», а также совместимых по интерфейсу ИС для дальнейшей обработки процессором. Кроме того, цифровой контроллер позволяет выводить данные непосредственно с выходов АЦП (минуя буферную память и интерфейс MPORT), например, в 1288ХК1Т (Digital Down Converter). Практическое применение микросхем возможно в таких областях как системы ввода изображения, в том числе системы тепловидения; радиосвязь; радиолокация; гидроакустические системы; измерительная техника; системы сбора данных; системы управления; системы промышленного контроля; и в других устройствах, позволяющих принимать и обрабатывать отсчеты АЦП в реальном времени. Макетные образцы микросхем 9008ВГ1Я имеют маркировку 1892ВГ1Я или 2008ВГ1Я. Основные характеристики тактовая частота АЦП 20 МГц; частота входного сигнала до 140 МГц; буферная память типа FIFO глубиной 4096х2 отсчетов; возможность непосредственного доступа к встроенным АЦП; интерфейс памяти, позволяющий имитировать режимы работы SRAM, SDRAM; 32/16-разрядный режимы работы интерфейса памяти MPORT с частотой до 100 МГц; возможность объединения микросхем в группы для совместной работы на одной выходной шине данных - до 8 микросхем в составе двух групп; пиковое потребление 800 мВт; питание: цифровое: 2.5 В ядро, 3.3В периферия; аналоговое: 3.3 В; допустимое изменение напряжения ±5%; диапазон рабочих температур от -60 до 85°C; корпус BGA-192, 17х17 мм, шаг 1 мм. Для заказа микросхем и по всем интересующим вопросам обращайтесь по телефону: (499) 729-7110 begin_of_the_skype_highlighting (499) 729-7110 end_of_the_skype_highlighting, доб.114; факс: (495) 913-3188. E-mail: market@elvees.com. Источник: Элвис Neobxodimo priwlech ser'eznie organizacionnie i finasowie resursi i po programme zameschenija dowesti 2*!4 bit *20 msps do 2*14 bit *200-300 msps
milstar: Быстродействующие 14-разрядные ЦАП с токовым выходом серии 1273 В статье описаны микросхемы быстродействующих широкополосных 14-разрядных ЦАП серии 1273 разработки ФГУП НИИЭТ, г. Воронеж. Эти ЦАП являются представителями семейства TxDAC и оптимизированы для использования в передающих трактах систем широкополосной связи, оборудовании связи, беспроводных локальных сетях, инструментальных системах, а также в контрольно-измерительной аппаратуре и устройствах прямого цифрового синтеза (DDS). Прототипами микросхем являются изделия фирмы Analog Devices. М икросхемы ЦАП и АЦП относятся к числу компонентов, наиболее широко распространенных на мировом рынке электроники, поскольку они объединяют цифровые и аналоговые блоки различных систем РЭА. Среди приборов этого класса важное место занимают быстродействующие ЦАП с разрядностью 8—16 бит, ориентированные, прежде всего, на беспроводные средства связи и инструментальные системы. Для реализации современного уровня требований к таким ЦАП необходимо решать задачи улучшения их динамических характеристик, а также повышения разрешения и скорости восстановления выходного сигнала. В работе [1] отмечается, что быстродействующие ЦАП для средств связи в большинстве своем выполняются с использованием сегментированной архитектуры на источниках тока (segmented current source architecture), обеспечивающей высокую точность установления сигнала. При этом помимо стандартных параметров, определяющих свойства быстродействующих ЦАП, например производительность, частота обновления выходных данных, время установления, интегральная (INL) и дифференциальная (DNL) нелинейность, вводятся и такие специальные параметры как SFDR — динамический диапазон, свободный от паразитных составляющих (гармоник), IMD — коэффициент интермодуляционных искажений, SNR — отношение сигнал/шум на частоте несущей и др. Разработка первого отечественного быстродействующего 14-разрядного ЦАП с сегментированной архитектурой на источниках тока 1273ПА4Т была выполнена ФГУП НИИЭТ в 2006 г. Производительность ЦАП составляет до 125 млн выб./с (MSPS). Прототипом микросхемы является AD9764 фирмы Analog Devices. В настоящее время проводится разработка еще трех типов ЦАП с подобной архитектурой — 1273ПА5У, 1273ПА6У и 1273ПА7Т. Микросхемы обеспечивают высокую производительность и имеют в составе различные дополнительные устройства, которые значительно расширяют их функциональные возможности. Сравнительные параметры всех четырех типов ЦАП приведены в таблице 1. http://www.russianelectronics.ru/developer-r/review/2190/doc/40461/ Автор: Валерий Скляр, зам. нач. отд., ФГУП НИИЭТ; Владимир Горохов, зам. гл. инженера, ФГУП НИИЭТ; Юрий Борисов, вед. инженер-конструктор, ФГУП НИИЭТ; Денис Горбунов, инженер-конструктор 1-й кат., ФГУП НИИЭТ; Сергей Битюцких, инженер-конструктор 1-й кат., ФГУП НИИЭТ
milstar: http://micro.ax-09.ru/present/micro_sibagatullin.pdf 2006 god 8bit AZP
milstar: http://www.analog.com/static/imported-files/tutorials/MT-025.pdf pushed the core technology to 14-bits with the release of the AD6644 14-bit 65-MSPS ADC in 1999, the AD6645 14-bit 80-MSPS ADC in 2001, and a 105-MSPS version of the AD6645 in 2003. Although these ADCs use the error-corrected pipelined subranging architecture, the internal building block core ADCs utilize the MagAMP™ architecture. Page
milstar: 16-Bit, 250MSPS ISLA216P25 The ISLA216P is a family of low power, high performance 16-bit analog-to-digital converters. Designed with Intersil’s proprietary FemtoCharge™ technology on a standard CMOS process, the family supports sampling rates of up to 250MSPS. • Total Power Consumption = 786mW @ 250MSPS Digital output data is presented in selectable LVDS or CMOS formats. Applications • Radar Array Processing SNR 72.1 db/363 mhz 71.1db/461 mhz 69.2db/605 mhz SINAD 71.6 69.2 65.7 ENOB 11.60 11.20 10.62 SFDR 81 db 73 db 67 db http://www.intersil.com/data/fn/fn7574.pdf Functional Description The ISLA216P25 is based upon a 16-bit, 250MSPS A/D converter core that utilizes a pipelined successive approximation architecture (Figure 18). The input voltage is captured by a Sample-Hold Amplifier (SHA) and converted to a unit of charge. Proprietary charge-domain techniques are used to successively compare the input to a series of reference charges. Decisions made during the successive approximation operations determine the digital code for each input value. Digital error correction is also applied, resulting in a total latency of 10 clock cycles. This is evident to the user as a latency between the start of a conversion and the data being available on the digital outputs. dlja srawnenija AD9467 ,wische 300 mhz parametri ne normirowanni ----------------------------------------------------------------------------------- http://www.analog.com/static/imported-files/data_sheets/AD9467.pdf pervij pok 2 volta ,wtoroj dlja 2.5 volta p-p analog input SNR 73.3/74.6 db /300 mhz SINAD 73.1 dbfs/ 74.4 ENOB 11.9/12.1 db SFDR 93/90 dBFS THEORY OF OPERATION The AD9467 architecture consists of an input-buffered pipe-lined ADC that consists of a 3-bit first stage, a 4-bit second stage, followed by four 3-bit stages and a final 3-bit flash. Each stage provides sufficient overlap to correct for flash errors in the preceding stage. The input buffer provides a linear high input impedance (for ease of drive) and reduces the kick-back from the ADC. The buffer is optimized for high linearity, low noise, and low power. The quantized outputs from each stage are combined into a final 16-bit result in the digital correction logic. The pipelined architecture permits the first stage to operate with a new input sample while the remaining stages operate with preceding samples. Sampling occurs on the rising edge of the clock. Each stage of the pipeline, excluding the last, consists of a low resolution flash ADC connected to a switched-capacitor DAC and an interstage residue amplifier (for example, a multiplying digital-to-analog converter (MDAC)). The residue amplifier magnifies the difference between the reconstructed DAC output and the flash input for the next stage in the pipeline. One bit of redundancy is used in each stage to facilitate digital correction of flash errors. The last stage simply consists of a flash ADC. The output staging block aligns the data, corrects errors, and passes the data to the output buffers.
milstar: Pipelineconverter . Opisanie prinzipov ot TI http://www.lte.eei.uni-erlangen.de/download/AUD/lesson10.pdf Pipeline ot TI 12bit 1 gsps AD5400 12bit 500/550 msps ADS5463 14 bit 400 msps ADS5474 16 bit 200 msps ADS5484/85
milstar: http://www.ll.mit.edu/publications/journal/pdf/vol12_no2/12_2widebandradar.pdf Bandwidths that are 10% of the radar’s carrier frequency are reasonably straightforward to implement (e.g., 500 MHz at C-band or 1000 MHz at X-band). Processing 500-MHz-bandwidth signals in some conventional pulse-compression scheme was not feasible with the technology available at the time of ALCOR’s inception. Consequently, it was necessary to greatly reduce signal bandwidth while preserving range resolution. This is accomplished in a timebandwidth exchange technique (originated at the Airborne Instrument Laboratory, in Mineola, New York) called stretch processing [4], which retains range resolution but restricts range coverage to a narrow thirtymeter window. In order to acquire and track targets and designate desired targets to the thirty-meter wideband window, ALCOR has a narrowband waveform with a duration of 10.2 мsec and bandwidth of 6 MHz. This narrowband waveform has a much larger 2.5-km range data window. During 1972 and 1973, Lincoln Laboratory devel-oped a 512-MHz-bandwidth (on a 1-GHz interme-diate frequency [IF]) t.e. 744 mhz -1256 mhz ------------------------------------- ALCOR operates at C-band (5672 MHz) with a signal bandwidth of 512 MHz that yields a range resolution of 0.5 m. (The ALCOR signal was heavily weighted to produce low range sidelobes with the concurrent broadening of the resolution.) Its widebandwidth waveform is a 10-мsec pulse linearly swept over the 512-MHz frequency range. High signal-tonoise ratio of 23 dB per pulse on a one-square-meter target at a range of a thousand kilometers is achieved
milstar: 1.28.09.1999 Maxim 8bit/1.5gsps/FLASH MAX108 2. 10/15/2003 Atmel/e2V 10bit/2gsps/FOLDING-INTERPOLATIG TS83102G0B 3.October 2009 TI 12 bit/1gsps/3 stage PIPELINE ADS5400 4. May 24, 2010 National Semiconductor/TI 2*12 bit *1.8 gsps ADC12D1800 FOLDING INTERPOLATING 5. xx.xx.201? XXX company introduce industry first single core 14 bit 1 gsps ADC architectur -XXX ? SNR = 70 dbc by Fin 700 ? 1000 mhz ? 1.28.09.1999 Maxim 8bit/1.5gsps/FLASH -------------------- September 28, 1999-Maxim Integrated Products introduces the MAX108 The MAX108 is the first 8-bit, 1.5Gsps monolithic ADC to achieve a typical 47dB SINAD and 54dB SFDR at 1.5GHz http://www.maxim-ic.com/company/newsroom/pr_products/show.mvp/npk/38 The MAX108 achieves a full 47dB SINAD and 54dB SFDR at 750MHz (Nyquist) input frequency. The MAX108 achieves this high performance through both innovative design and the use of Maxim's proprietary 27GHz GST-2 IC bipolar process. An integrated, fully differential input track/hold (T/H) combined with precision laser-trimmed resistors produce a typical INL and DNL of less than ±0.25LSB, a full-power bandwidth of 2.2GHz, and less than 0.5ps aperture jitter. 2. 10/15/2003 Atmel/e2V 10bit/2gsps/FOLDING-INTERPOLATIG --------------------- 10/15/2003 - Atmel® Corporation (Nasdaq: ATML) The TS83102G0B is the first ADC available that combines 10-bit resolution, 2 Gsps maximum The TS83102G0B delivers excellent performance while only dissipating 4.6W. SFDR (spurious free dynamic range) is 60dBFS at 1.4Gsps/700MHz input frequency, and still in the 55dBFS range at 2Gsps / 2GHz input frequency. Two-tone third order intermodulation distortion is 65dB at 1.4Gsps over a 500MHz band centered around 1GHz, allowing to digitise high IF broadband signals with adjacent channels with a very low level of parasitic spectrum components. It is further complemented by added features such as data ready output, asynchronous data ready reset and gain controls. 3.October 2009 TI 12 bit/1gsps/3 stage PIPELINE ----------------------------------------------------------- http://www.electronicsweekly.com/Articles/28/10/2009/47279/ti-unveils-industrys-first-12bit-1gsamples-adc.htm TI unveils industry's first 12bit 1Gsample/s ADC Steve Bush Wednesday 28 October 2009 14:01 Texas Instruments has unveiled industry's first 12bit 1Gsample/s ADC, the ADS5400. A buffered front-end simplifies external circuit design, and fast sampling means up to four can be used together for 4Gsample/s and 2GHz bandwidth. Preceded by bandpass filter, the device can also be used to under-sample, covering 500MHz-1GHz, 1.0-1.5GHz, or 1.5-2.0GHz. Spurious-free dynamic range (SFDR) is, according to Beckemeyer, 77-78dB at DC, 72-73dB at 1GHz, and in the 60dB range at 2GHz. Sample-and-hold and analogue bandwidth are sufficient to cover DC-2GHz in one go by running four converters in parallel. On-chip hardware allows two or four devices to be interleaved. 4. May 24, 2010 National Semiconductor/TI 2*12 bit *1.8 gsps FOLDING INTERPOLATING ------------------------------------------------------------------------------ http://www.redorbit.com/news/technology/1869464/national_semiconductor_introduces_industrys_fastest_12bit_adc/ Introduces Industry’s Fastest 12-bit ADC SANTA CLARA, Calif., May 24 /PRNewswire-FirstCall/ — National Semiconductor Corp. (NYSE: NSM) today introduced the Industry’s fastest 12-bit analog-to-digital converter (ADC). At 3.6 Giga-samples per second (GSPS), the ADC12D1800 is 3.6 times faster than any other available 12-bit device. The ADC’s dynamic performance of -147 dBm/Hz noise floor, 52 dB noise power ratio (NPR) and -61 dBFS intermodulation distortion (IMD) enables a new generation of software-defined radio (SDR) architectures and applications. 5. xx.xx.201? XXX company introduce industry first single core 14 bit 1 gsps ADC SNR = 70 dbc by Fin 700 ? 1000 mhz ? Power consumated = until 5 watt ?
milstar: Time interleveaved 14 bit *400 msps*4 http://www3.ntu.edu.sg/temasek-labs/images/research/spsoc/TIADCV.pdf fin 220 mhz/580 mhz SNR -65.6db/59.7db SFDR - 78db/68.7dbc ENOB -10.6/9.6 bit dlja srawnenija isxodnij ADS5474 bez interleaving http://www.ti.com/lit/ds/symlink/ads5474.pdf 14 bit 400 msps 230 mhz/650 mhz SNR- 69.8/67.5 dbfs SFDR -80/60 dbc ENOB 10.9 bit/ ....
milstar: http://www.tekmicro.com/PDFs/MuPuRF_Radar.pdf The practical signal bandwidth is close to 1GHz and the range resolution is close to 15cm. The core of the TRITON VXS-1 is a Xilinx Virtex-II Pro FPGA circuit along with a 10bit ADC and a 12bit DAC. Both converters can operate at 2 GSamples/sec, giving a Nyquist digital signal bandwidth of 1 GHz. The analog 3 dB-bandwidth extends from 3 MHz to 3 GHz.
milstar: http://spdevices.com/index.php/products2/adx4-evm-2000-12 Single-tone at 190 MHz. Fs=2 GS/s, SFDR=82 dBc, ENOB=10.3 bits. ADX4-EVM-2000/12 4 x 12-bit ADCs interleaved to 2000 MSPS ################# http://www.intersil.com/converters/ADC_ref_design.asp Intersil 2GSPS Reference Design By interleaving Intersil's low power, high sample rate ADCs, it is possible to achieve a combination of ultra-high sample rate and very high dynamic range that is not available in today’s stand-alone ADCs. This reference design demonstrates the performance attainable by combining Intersil's ADC technology and SP Devices interleaving algorithms. In this design, 4 ISLA112P50 12-bit, 500 MSPS analog-to-digital converters are interleaved to sample at a rate of 2.0 GSPS. At this sampling rate, the reference design provides over 6dB more SNR and 13dB better SFDR than the best alternative stand-alone ADC. Collaboration of Intersil and SP Devices Demonstrates 4-way Interleaving of Intersil 500MSPS ISLA112P50s Sample Rate: 2.0 GSPS Resolution: 12 Bits Interleave Correction Details SP Devices’s ADX4 provides real-time, digital, FPGA based digital interleave correction of four ISLA112P50s Performance SNR = 65.5 dBfs @ Fin = 190MHz, a 6dB improvement over current best standalone 2GSPS ADCs SFDR = 82 dBc @ Fin = 190MHz, a 13dB SFDR improvement over current best standalone 2GSPS ADCS Zdes Intersil nechesten ------------------------------------ 12 bit GSPS ADC - 1-1.15 -1.8 GSPS ot TI,E2V,National/TI dajut swoi dannie dlja 1 -1.2 ghz-1.33 ghz -1.448 ghz SNR 56-57 db, SFDR 65-66 db w otlichii ot Intersil na 190 mhz 65.5 dBFS ############################## ili 63.5 db na 900 mhz
milstar: SP Devices' time-interleaving technology in module from Texas Instruments TI introduces 14-bit, 800-MSPS digitizer solution leveraging industry's fastest data converters DALLAS -- Sept. 4, 2008 -- Texas Instruments Incorporated (TI) (NYSE: TXN) today introduced an evaluation module (EVM) that combines TI's fastest 14-bit analog-to-digital converters (ADCs) in an interleaved fashion with a Xilinx® Virtex®-5 FPGA to create the best-performing high-speed digitizer solution in the market. The FPGA comes pre-installed with SP Devices' proprietary time-interleaving technology to eliminate interleaving spurs, which enhances performance and facilitates rapid system-level evaluation for wireless communications, military, test and measurement applications. The EVM joins TI's portfolio of support tools for customers using high-speed data converters in wide-bandwidth applications. (See www.ti.com/ads5474adx-evm-pr.) The ADS5474ADX-EVM incorporates two of TI's ADS5474 ADCs, a Xilinx Virtex-5 FPGA and SP Devices' proprietary time-interleaving technology to deliver an 800-MSPS ADC solution. The SP Devices' software continuously monitors the system and removes ADC gain, clocking and temperature mismatches to reduce the interleaving spurs below the ADC harmonic spurs. By reducing the interleaving spurs, the software increases spurious free dynamic range (SFDR) from 45.78 dBc to 86.44 dBc for a 70-MHz input signal. ################################################## Na dannoj Fin y 16 bit 250 msps ADC Intersil 216p25 ili Analog Device AD9467 SFDR 93-95 dbc "Addressing the industry's ever-increasing demand for higher sampling speeds and extended bandwidth is important to us," said Jonas Nilsson, CEO of SP Devices. "Combining SP Devices' innovative interleaving technology with TI's market-leading data converters allows us to extend performance boundaries of high-speed ADCs, which will enable exciting new applications including multi-carrier systems, software-defined radio, advanced imaging and beyond." In addition to improved performance for these complex systems, the EVM simplifies evaluation and helps designers bring end systems to market faster. For instance, the continuous monitoring of the ADC's mismatch eliminates the need for an off-line re-calibration routine to account for changes in temperature or other environmental factors, significantly reducing system evaluation and design time. "With this latest EVM, customers can focus on prototyping advanced architectures to optimize system-level performance in these complex applications, rather than concentrating on developing an interleaving solution," said Mark Stropoli, worldwide marketing manager for TI's High Speed Products. Availability and packaging The ADS5474ADX-EVM is available today from TI at www.ti.com/ads5474. Pricing for the EVM is $1,999. The ADS5474ADX-EVM is the latest addition to TI's world-class high-speed and precision data converter tools designed to address a range of applications. For more information, visit the Analog eLabTM Design Center at www.ti.com/analogelab. Further information about SP Devices' interleaving technology is available at www.spdevices.com.
milstar: High Sensitivity Receiver Applications Benefi t http://cds.linear.com/docs/Design%20Note/DSOL44.pdf The high sampling rate of the LTC2208 provides an advantage when used in oversampling applications, using processing gain to improve the receiver’s SNR performance. Capturing a signal bandwidth of 30MHz requires an ADC with a sample rate of at least 60Msps. However if the signal was sampled at a higher rate of 120Msps the broadband noise fl oor is reduced by 3dB as given by the following equation
milstar: 1.1 GHz Bandwidth ADC Enables High IF-Sampling for Space-Based Narrowband Communications Applications http://www.national.com/assets/en/other/ProdBrief_ADC14155.pdf
milstar: It achieves a small-signal SNR of 72 dBFS and a SFDR greater than 90 dBFS with a 169 MHz input frequency. Large signal performance yields a SNR of 68.3 dBFS and SFDR of 77 dBFS at 169 MHz. In http://webench.national.com/rd/RD/RD-146.pdf High IF Receiver Reference Design
milstar: http://www.ewh.ieee.org/r6/scv/ssc/Dec1208.pdf esche odin linearizator str 35 dlja 14 bit 155msps stojkogo k radiazii ational SFDR 85 db na 470 mhz protiv 75 db do Verojatno oschibka w Fin ne 470 a 270 mhz http://www.ti.com/lit/ds/symlink/adc14155qml.pdf
milstar: Performance of subband HFB-based A/D converters http://hal.archives-ouvertes.fr/docs/00/26/11/64/PDF/IEEE_ISSPa_2007_Sharjah.pdf Filter-bank Design for Sub-band ADC http://www.stanford.edu/~arkam/letter_subband.pdf
milstar: Performance of an IF sampling ADC in receiver applications David Buchanan Staff Applications Engineer Analog Devices, Inc http://www.engr.sjsu.edu/rmorelos/ee160s04/2001APR03_AMD_RFD_TAC.pdf
milstar: http://www.eleceng.adelaide.edu.au/Personal/mtrinkle/IRS2006.pdf SNR Considerations for RF Sampling Receivers for Phased Array Radars Matthew Trinkle*
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