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Operazionnie ysiliteli ,ZAP/AZP & (ïðîäîëæåíèå)
milstar: 1941: First (vacuum tube) op-amp An op-amp, defined as a general-purpose, DC-coupled, high gain, inverting feedback amplifier, is first found in US Patent 2,401,779 "Summing Amplifier" filed by Karl D. Swartzel Jr. of Bell labs in 1941. This design used three vacuum tubes to achieve a gain of 90dB and operated on voltage rails of ±350V. ###################################################### It had a single inverting input rather than differential inverting and non-inverting inputs, as are common in today's op-amps. Throughout World War II, Swartzel's design proved its value by being liberally used in the M9 artillery director designed at Bell Labs. ######################################################################### This artillery director worked with the SCR584 radar system to achieve extraordinary hit rates (near 90%) that ####################################################################### would not have been possible otherwise.[3] ########################### http://en.wikipedia.org/wiki/Operational_amplifier
milstar: Multiple A/Ds versus a single one: pushing high-speed A/D converter SNR beyond the state of the art Thomas Neu and Grant Christiansen, Texas Instruments. Inc. 7/4/2007 5:54 PM EDT (Note: an edited version of this article appeared in Planet Analog magazine, June 24, 2007. This online version includes formulas and derivations that did not appear in the print version.) The wireless communications field is constantly demanding faster and higher resolution high-speed data converters to enable them to process more bandwidth (allowing more channels) with greater resolution. One way to further advance state-of-the-art analog-to-digital converters (ADC) is to average multiple high-speed ADCs to increase the dynamic range. With two ADCs, for example, the overall signal-to-noise ratio (SNR) can be improved by up to 3 dB; with three converters, it can be as much as 4.8 dB. -------------------------------------------------------------------------------------------- Theoretically, the SNR can be increased by 3 dB (one-half-bit) with two different methods. ------------------------------------------------------------------------------------------------------- One option is to double the sampling rate and digitally filter the output (e.g., with an FIR decimation filter). The second option is to parallel two ADCs and simply average the digital output. At times, doubling the sampling rate is the less desirable option because faster ADCs may not yet be available. They may also start out with a lower SNR and often times are higher power than two slower ADCs. Furthermore, a faster sampling clock with low jitter is required. -------------------------------------------------------------------------------------------------------------------------------------------------- This article shows the actual results of combining three TI ADS5546 converters (14-bit, 190 Msps), using the second option of paralleling the ADCs, and it addresses the clock jitter requirement which engineers face with the implementation. ------------------------------------------------------------------------------------------------------ Setup The concept of averaging the output of separate ADCs for SNR improvement was verified using three ADCs tied to an FPGA, which then outputs the conversion results of each individual ADC or two or three ADCs averaged together, Figure 1. By using three ADCs instead of one, the SNR ideally improves by 4.8 dB, as derived below, which boosts the 14-bit ADC (SNR ∼74dB) to a 16-bit ADC ################################################################################################## level (SNR ∼79dB). ############# Ostanetsja li wse ostlanoe ? W predleax trebowanij Esli da .to mozno wzjaz 3 12 bit po 1-1.8 gsps i poluchit 14 bit s input frequency 1000 mgz AFAR PAK FA/ F-22 imeet 2 rezima SAR ,gde trebuetsja takaja polosa pri neuschej 8 -10 ghz 1. SAR s rar .sposobnostju 250 mm na suche 2. Poisk periskopa PLA Odno preobrazowanei chastoti i srazu AZP Po nekotorim publichnim dannim w PAtriot PAC-3 16 bit AZP The analog input signal was split and fed into three ADCs which were sampled with a common clock source. An FPGA performed the averaging function as well as a level translation of the digital output from DDR-LVDS to LVTTL (double-data-rate, low-voltage differential signal to low-voltage TTL). Figure 1: Block Diagram of System to Average Multiple ADC Outputs (Click to enlarge image) The averaging technique reduces uncorrelated white noise, but has no effect on distortions inherent to the ADC design that might be common to all three ADCs. If, for example, the ADC creates a large third-order distortion product, it will show up in each ADC used and averaging won't reduce it. Therefore, averaging only improves SNR, but not spurious free dynamic range (SFDR). The formulas and derivations used to determine the maximum SNR gain for the two methods described above (doubling the sample rate and averaging multiple ADCs) are discussed in the addendum at the end, "Theory." Measurements In order to verify the SNR gain, a board was designed containing three ADS5546 ADCs (14-bit, 190 Msps) and an FPGA that was used to perform a 3:1 averaging function. Using two or three standalone ADC evaluation modules (EVM) for this experiment usually doesn't work as well, because noise coupled into the cable assembly is correlated and, therefore, doesn't average out. Furthermore, if the cables are not matched very well, skew between ADCs adds phase mismatch and further degrades the overall SNR. Unfortunately, the chosen input matching network design was not optimized. The trace impedance was not adjusted properly to the transformer and the split input traces were not properly matched. Due to this input mismatch, the input signal was attenuated at frequencies above 60 MHz with one exception. Around 150 MHz, the input circuitry seemed to work very well. Therefore, some of the measurements were taken with an input amplitude as low as -6 dB, and were mathematically adjusted to -1 dB full scale (FS) afterwards in the following manner. First, with only one ADC active, the SNR performance was measured and compared to the ADS5546 data sheet performance at the lower input amplitude. Then the measurement with three ADCs active was adjusted by the difference. This adjustment seems justified as the 150 MHz data point is right in line with the resulting values, Figure 2. Figure 2: SNR Comparison between ADS5546 Data Sheet Values, Single ADC and Triple ADC (Click to enlarge image) The adjusted measurements show a consistent 4-or-greater dB improvement across various input frequencies when comparing it to 'single ADC' data. Even at the higher input frequencies, the measured and calibrated values within one-half dB of the theoretical values with the exception of device number three. The noticeable SNR roll-off is due to the clock-jitter limitation which is prevalent in any ADC, as derived in the next section. Clock jitter requirements The final SNR at the output depends on the input frequency and is primarily limited by the thermal noise of the ADCs and the aperture jitter of the sampling clock. As derived earlier, averaging the SNR of three ADCs improves all uncorrelated noise sources by ∼4.8 dB which applies to the thermal noise term, as well as the internal aperture jitter of the ADC. The ADS5546 data sheet lists the following specifications: •Thermal noise ∼74 dB (=SNR at low input frequency where SNR is thermal noise limited) •Aperture jitter ∼150 femtoseconds (fs) Therefore, when averaging the outputs of three ADCs sampling the same signal, the overall thermal-noise contribution is reduced from 74 dB to 78.8 dB and the ADC aperture uncertainty from 150 fs to 86 fs (1.50 fs · 10-4.8/20). The sampling jitter comprises the internal aperture jitter of the ADC and the jitter of the external clock source (common to all three ADCs when averaging). http://www.eetimes.com/design/automotive-design/4009960/Multiple-A-Ds-versus-a-single-one-pushing-high-speed-A-D-converter-SNR-beyond-the-state-of-the-art
milstar: http://www.schoenduve.com/assets/Maxtek_DCM_Brochure.pdf Maxtek 8 -bit ADC 10 gigasample/sek 5 ghz 0.18 microna SiGE BiCMOS process Maxtek customers include Top-30 defense contractors
milstar: http://www.ausairpower.net/APA-Zhuk-AE-Analysis.html The new radar would use a new antenna and Analogue/Digital Converter (ADC) design, ######################################################## a new exciter/driver stage, but retain the existing receiver chain, processors, and coherent oscillator. Intended improvements for a production design include better processing and a broadband programmable master oscillator module. The latter is to provide many of the advanced capabilities seen in the latest Western AESAs. Zhuk AE Design Philosophy - A Radar Engineering Perspective Phazotron's engineers have provided some excellent insights into the design philosophy and achievable performance, and performance growth, in the Zhuk AE design [click for more ...]. Less fortunately, the original works were not well translated into English, seeing much technical language translated improperly, making the original work less than comprehensible to readers without exposure to radar engineering. The starting point for the Zhuk AE design was the existing Zhuk MF, as Phazotron's engineers correctly assessed that the cost and risk of an entirely new design would be too great. In this respect they followed the model used by Raytheon in the APG-79 and Northrop-Grumman in the APG-80, rather than the 'all new' approach seen with the Northrop Grumman APG-77. The aim was to re-engineer the PESA design for a new liquid cooled AESA, retaining as much of the PESA design as was feasible. Phazotron appear to be exploring digital beamforming techniques in what Chief Designer Dolgachev describes as a two stage processing scheme, with initial beamforming performed in the AESA, and additional beamforming in the digital receiver, downstream of the ADC stage. ################################################################################# Adaptive nulling of mainlobe jammers is also raised as a benefit of the AESA design. Other important determinants of performance such as oscillator parameters and ADC dynamic range and noisiness ######################################################################### have been conveniently omitted from the public disclosure.
milstar: http://www.analog-europe.com/en/solutions_for_time_interleaving_ultra-high-speed_adcs_at_the_pcb_level?cmp_id=7&news_id=221601117 Technology News Solutions for time interleaving ultra-high-speed ADCs at the PCB level November 04, 2009 | | 221601117 This article explores the inherent technical challenges associated with time interleaving ADCs and provides useful system-design guidelines. Synchronously sampling analog signals with time-interleaved analog/digital converters (ADCs) at billions of times per second is a considerable technical challenge, and requires very carefully designed mixed-signal circuits. In essence, the goal of time interleaving is to multiply the sampling frequency by the number of converters used, but without impacting resolution and dynamic performance. This article explores the inherent technical challenges associated with time interleaving ADCs and provides useful system-design guidelines. New and innovative component features and design techniques that address the known issues are presented. Measured FFT results from a 7 Gsps (gigasamples per second), two-converter chip 'interleaved solution' are provided. Finally, applications-support circuitry necessary to achieve high performance is described, including clock sources and drive amplifiers. Increasing need for higher sampling speeds When and why is it an advantage to increase sampling frequency? There are several answers to this question. Essentially an ADC's sampling speed directly determines the instantaneous bandwidth that may be digitized in one sampling instant. The Nyquist and Shannon sampling theorems state that the maximum available sampling bandwidth (BW) is equal to half the sample frequency (Fs). A 3-Gsps ADC enables 1.5 GHz analog-signal spectrum to be sampled in one sampling period. Doubling the sampling speed also doubles the Nyquist bandwidth to 3 GHz. The resultant multiplication in sampling bandwidth gained by time interleaving is beneficial in many applications. For example, radio-transceiver architectures can increase the number of information signal carriers, and therefore, system data throughput can be expanded. Increasing Fs also improves resolution in laser imaging detection and ranging (LIDAR) measurement systems, ######################################################################## which operate on the principle of time of flight (TOF). The uncertainty in TOF measurements can be reduced by decreasing the effective sampling-clock period. Digital oscilloscopes also require high Fs to input frequency (FIN) ratios for accurately capturing complex analog or digital signals. Fs must be several multiples of FIN(max) to capture the harmonic components of FIN. For example, if the oscilloscope sampling frequency is not sufficiently high, a square wave will appear sinusoidal if the higher-order harmonics are outside the Nyquist bandwidth of the ADC. Figure 1 illustrates the benefit in doubling sampling frequency in an oscilloscope front-end. The 6 Gsps sampled waveform is a much more accurate representation of the sampled analog input. Many other test instrumentation systems, such as mass spectrometers and gamma ray telescopes, depend on high over-sampling to FIN ratios for pulse-shape measurement. Figure 1: Time-domain measured plots of a 247.77 MHz signal sampled at 3 Gsps and 6 Gsps. (Click on image to enlarge) There are also other advantages gained by increasing sampling frequency. Over-sampling signals also enables processing-gain benefits in the digital domain with the use of digital filtering. This is because the ADC noise floor can be spread over a larger output bandwidth. Doubling the sampling rate, for a fixed input bandwidth, results in a 3 dB improvement in dynamic range. Every further doubling of the sampling frequency provides an additional 3 dB of dynamic range. Challenges with time interleaving The main challenges with time interleaving are accurate phase alignment of sampling-clock edges between channels, and compensating for manufacturing variations that inherently occur between ICs. Accurately matching the gain, offset and clock phase between separate ADCs is very challenging, especially as these parameters are frequency dependant. Unless precise matching of these parameters is achieved, dynamic performance and resolution will be reduced. The three main sources of error are illustrated in Figure 2. Figure 2: Gain, offset and timing errors introduced by interleaving ADCs (Click on image to enlarge) Sampling-clock phase adjustment Generally, a two-channel interleaved-converter system requires that the ADC input-sampling clocks are time shifted by ½ clock period. However, the National Semiconductor ADC083000 ADC architecture uses on-chip interleaving and operates with a clock frequency equal to half the sample rate, i.e. 1.5 GHz to achieve 3 Gsps. Therefore, for a two-channel system employing two ADC083000's, the ADC input sampling clock edges must be time shifted by ¼ clock period or 90° with respect to each other. This corresponds to 166.67 picoseconds for a 1.5 GHz clock. The clock-signal trace lengths can be calculated to meet, with some accuracy, the ¼ clock-period phase shift. For FR-4 PCB material, a signal propagates at 20 cm/ns, i.e. 1 cm in 50 ps. For example, if the clock trace to one ADC is 3 cm longer than the other, this will result in a 150 ps phase shift. The challenge is to accurately meet the additional 16.67 ps time shift. The ADC083000 has an integrated clock-phase adjustment feature that allows the user to add a delay to the input-sampling clock to shift its phase, relative to another ADC's sampling clock. The clock phase of the ADC can be adjusted manually through two internal registers over an SPI bus. The phase shift is only possible in one direction, increasing delay. The designer should determine which of two discrete ADC's is "ahead" and adjust its phase so that its sample edges are 90° between the other ADC's sample edges. Sub-picosecond adjustment resolution is provided. Channel-to-channel gain and offset matching In a two-converter interleaved system, the error voltages generated by channel gain mismatches result in image spurs that are located at Fs/2 – FIN and Fs/4 ± FIN (assuming the input signal is within the first Nyquist band). An 8-bit converter has 28 or 256 codes. Assuming the converter full scale input range is 1 Vp-p, the LSB size is: 1 V/256 = 3.9 mV. We can then calculate that the required gain matching for ½ LSB accuracy is 0.2%. The input full-scale voltage or gain of the ADC083000 can be adjusted linearly and monotonically with a 9-bit data value. The adjustment range is ???20% of the nominal 700 mVp-pdifferential value, or 560 mVp-pto 840 mVp-p. 840 mV – 560 mV = 280 mV. 29 = 512 steps. 280 mV/512 = 546.88 μV This degree of fine adjustment allows greater than 0.2% gain matching as required above. Offset mismatching between adjacent channels generates an error voltage that results in an offset spur that is located at Fs/2. Since the offset spur is located at the edge of the Nyquist band, designers of two-channel systems can typically plan their system frequency around it, and focus their efforts on gain and phase matching. However, let us assume that the required offset matching is also ½ LSB. The input offset of the ADC083000 can be adjusted linearly and monotonically from a nominal zero offset to 45 mV of offset with 9-bit resolution. Thus, each code step provides 0.176 mV of offset and the 9-bit resolution enables ½ LSB accuracy. Synchronization of digital outputs Synchronizing the output data streams from both ADCs is essential to realize the combined sampling speed and bandwidth. In other words, meaningful data capture is not possible if loss of output synchronization between individual converters occurs. The gigasample-range ADCs demultiplex ('demux') the output data to reduce the digital output data rate. The user has the option of 'demuxing' the data rate by 2 or 4, depending on the data-handling capacity of the FPGA technology used. The output capture clock (DCLK) is also divided and can be configured in SDR or DDR mode. However, demuxing introduces an additional consideration because there is now added uncertainty regarding the correspondence between the input sampling clock and the DCLK output of each ADC. To overcome this, the ADC083000 has the capability to precisely reset its sampling clock input to a DCLK output relationship, as determined by the user-supplied DCLK_RST pulse. This allows multiple ADCs in a system to have their DCLK (and data) outputs transition at the same time with respect to the shared input clock they use for sampling, enabling the synchronization between multiple ADCs. Digital interleaving techniques Analog calibration is a proven method to deliver high dynamic range, and highly integrated monolithic solutions and the integrated clock phase, gain and offset adjustment features described have proven to provide a high level of accuracy. Some potential alternatives to analog calibration techniques are digital correction algorithms that operate on the interleaved data. These engines seek to correct data converter mismatches in the digital domain without requiring any analog offset, gain, or phase correction. Ideally, these algorithms can operate independently without any calibration or prior knowledge of the input signal. Also, the time to converge on the digital offset, gain, and phase correction factors is a key system metric. One digital post-processing engine that has been demonstrated to meet these criteria, is an algorithm developed by SP Devices, Inc. SP Devices' ADX technology continuously provides a background estimate of the gain, offset and time skew errors of the ADCs without the need for any special calibration signal or post-production trimming. This algorithm has been demonstrated to correct both static and dynamic mismatch errors. The ADX technology estimates the error and reconstructs the signal with all mismatch errors suppressed. The error-correction algorithms of the IP-core operate effectively independent of input signal type. The result of this digital signal processing is that the time-interleaved spectrum out of the ADX core will have no apparent mismatch-related interleaving distortion spurs. The SP Devices algorithm has been demonstrated on a reference board featuring two ADC083000 3 Gsps, 8-bit ADCs from National Semiconductor. The data converters are interleaved using the ADX technology embedded in the on-board FPGA. The block diagram of this 7 Gsps digitizer card is shown in Figure 3. Figure 3: Block diagram of ADQ108 system with LMX2531 and LMH6554 (Click on image to enlarge) Figure 4 is a performance plot of the output spectrum from the SP Devices ADQ108 data acquisition card. It should be noted that that peak spurious components are due to harmonic distortion and the interleaving spurs have been dramatically reduced. (Further details on the data acquisition card can be found here.) Figure 4: Combined ADC spectrum with ADX implemented (Click on image to enlarge) Ultra-high-speed ADC support circuitry In order to achieve the high level of performance that can be attained using data converters such as the ADC083000, it is necessary to ensure that the supporting circuitry has performance comparable to the data converter itself. Key elements of support circuitry include: 1. High-performance, low-jitter clock sources 2. Highly linear, low-noise amplifiers or baluns to drive the ADC inputs The LMX2531 or LMX2541 clock synthesizers are recommended for generating the low-jitter ADC clock signal and LMH6554 for driving the ADC analog inputs. The LMX2531 integrates a PLL and VCO and provides a noise floor better than –160 dBc/Hz. The IC is available in several different versions to accommodate different frequency bands from 553 MHz to 2790 MHz. For even better high-input-frequency SNR performance, the lower phase noise LMX2541 is recommended as a suitable clock source. The LMX2541 provides less than 2 milliradians (mrad) root-mean-square (rms) noise at 2.1 GHz and 3.5 mrad rms noise at 3.5 GHz. The LMX2541's PLL offers a normalized noise floor of –225 dBc/Hz and can be operated with up to 104 MHz of phase-detector rate (comparison frequency) in both integer and fractional modes. The LMH6554 is the industry's highest-performance differential amplifier. Its low-impedance differential output is designed to drive ADC inputs and any intermediate-filter stage. This wideband, fully differential amplifier drives 8- to 16-bit high-speed ADCs with 0.1 dB gain flatness up to 800 MHz, SFDR of 72 dBc at 250 MHz, and low input-voltage noise performance of 0.9 nV/sqrt Hz. The LMH6554 delivers 16-bit linearity up to 75 MHz when driving 2 Vp-p into loads as low as 200 Ω. With external gain-set resistors and integrated common-mode feedback, the LMH6554 can be used in differential-to-differential or single-ended-to-differential configurations. The amplifier provides large signal bandwidth up to 1.8 GHz, 8 dB noise figure and a slew rate of 6200 V/μs. Figure 5 shows a typical block diagram implementation using the above-mentioned supporting components. Figure 5: Typical system block diagram using high-end components (Click on image to enlarge) Summary The challenges associated with interleaving high-speed ADCs and several approaches to addressing these issues have been presented. Maintaining excellent dynamic performance beyond 6 Gsps is now possible due to advancements in interleaving methodologies, low-jitter clock sources and high-performance amplifiers. About the author Paul McCormack is a senior applications engineer in National Semiconductor Corporation's High-Speed Signal Path Group in Europe. He received his Masters degree in Electrical and Electronic Engineering from the Queen's University of Belfast.
milstar: K stat'e wische http://www.national.com/pf/AD/ADC083000.html#Overview ADC083000 8-Bit, 3 GSPS, High Performance, Low Power A/D Converter from the PowerWise® Family http://www.national.com/ds/DC/ADC083000.pdf Resolution 8 Bits ■ Max Conversion Rate 3 GSPS (min) ■ Error Rate 10-18 (typ) ■ ENOB @ 748 MHz Input 7.0 Bits (typ) ■ SNR @ 748 MHz 44.5 dB (typ) ■ Full Power Bandwidth 3 GHz (typ) ■ Power Consumption — Operating 1.9 W (typ) — Power Down Mode 25 mW (typ)
milstar: There are also other advantages gained by increasing sampling frequency. Over-sampling signals also enables processing-gain benefits in the digital domain with the use of digital filtering. This is because the ADC noise floor can be spread over a larger output bandwidth. Doubling the sampling rate, for a fixed input bandwidth, results in a 3 dB improvement in dynamic range. Every further doubling of the sampling frequency provides an additional 3 dB of dynamic range. ######################### Challenges with time interleaving The main challenges with time interleaving are accurate phase alignment of sampling-clock edges between channels, and compensating for manufacturing variations that inherently occur between ICs. Accurately matching the gain, offset and clock phase between separate ADCs is very challenging, especially as these parameters are frequency dependant. ############################################### Unless precise matching of these parameters is achieved, dynamic performance and resolution will be reduced. The three main sources of error are illustrated in Figure 2. ###############
milstar: 4*14 bit ADC interleaved http://spdevices.com/index.php/products2/adx4-evm-1600-14 Single-tone at 62 MHz. Fs=1.6 GS/s, SFDR=88 dBc, ENOB=11.1 bits. ADX EVM is a series of evaluation cards that demonstrate the power of SP Devices interleaving algorithms in various environment and applications. The ADX EVMs show how distortions related to interleaving such as time-skew, offset- and gain- errors are corrected. Corrections are made transparently and in real time without any need of calibration signals. The correction algorithm support a resolution of up to 16 bits, with a preserved SFDR of up to 95 dB, depending on the properties of the specific ADC array. The ADX EVM evaluation card is equipped with four, 14-bit, interleaved AD-converters demonstrating the capabilities of SP Devices IP block for interleaving of high-speed AD-converters. ADX EVM uses a Xilinx V5 series SX 50T FPGA for the signal processing of the interleaving algorithms and for storing of data batches used for evaluation of the algorithm. The card has a USB 1.1 port for communication with the FPGA and a on board memory of 64 kSample. Setup and control of the evaluation card is made by the included software ADCaptureLab. The software contains useful analysis tools such as time series and FFT plots to facilitate the evaluation of the IP-block for the target application. The ADX EVM is delivered with a time limited license and is intended for evaluation purposes only. The ADX EVM may also be delivered as part of an ADX Design Kit for FPGA IP as a platform for initial development. ##################### US Navy Chooses the ADQ412 TIGER Digitizer Thursday, 16 September 2010 17:00 With its unique combination of high sample rate and high resolution, the ADQ412 TIGER was the natural choice for the US Navy. Boasting an impressive sample rate of 3.6 Giga samples per second (GSPS) and 12 bits vertical resolution the Naval Surface Warfare Center Panama City Division (NSWCPCD) found its ideal digitizer candidate in the ADQ412 TIGER. Visit the ADQ412 TIGER product page by clicking here, and to read more from the US Navy, click here. http://spdevices.com/index.php/company/news-archive/159-us-navy-chooses-spd http://spdevices.com/index.php/adq412tiger
milstar: DX - Interleaving Technology Time‑interleaving of analog‑to‑digital converters (ADCs) is a way to increase the overall system sample rate by using several ADCs in parallel. The challenge is to handle the mismatch between the individual ADCs, especially at higher frequencies. http://spdevices.com/index.php/interleaving Higher speed The SP Devices interleaving technology provides our customers with a method of increasing the sampling rates of their A/D solutions. The interleaving process involves the signal being sampled at different times by one of a number of parallel ADCs. The overall sampling rate is in this way multiplied by the number of ADCs. Handling the mismatch The challenge with interleaving is to correct for the manufacturing variations of the characteristics of the individual ADC, in order to obtain the optimal resolution. The variation after correction must be less than 0.01% in order to achieve the successful interleaving of a typical 14‑bit ADC! Furthermore, these variations depend on temperature and age, making the corrections required even more complex.
milstar: 1. the goal of time interleaving is to multiply the sampling frequency by the number of converters used, but without impacting resolution and dynamic performance. http://www.eetimes.com/design/analog-design/4010407/Solutions-for-time-interleaving-ultra-high-speed-analog-digital-Converters-at-the-PCB-level 2.Doubling the sampling rate, for a fixed input bandwidth, results in a 3 dB improvement in dynamic range. Every further doubling of the sampling frequency provides an additional 3 dB of dynamic range. ######################### http://www.analog-europe.com/en/solutions_for_time_interleaving_ultra-high-speed_adcs_at_the_pcb_level?cmp_id=7&news_id=221601117
milstar: Manuscript received September 15, 1998. This work was supported in part by US Air Force and ONR. ##################################### Mnogo russkix imen ,mozet w Rossii esche chto-to ostalos .... http://www.hypres.com/papers/ECB-01.pdf In our experiments we have achieved full functionality of several 14-bit ADC chips using two-channel race arbiters at speeds exceeding 10 GS/s. Fig.6 shows oscilloscope photos of the outputs of bits 1-8 in such an ADC operating at 11.5 GS/s with and without dither. (The dither is a low-amplitude sinewave having the ADC output sampling frequency, so it is completely suppressed by the decimation filter). It is seen that dither has a profoundly positive effect on the ADC operation for slowly changing signals [1] S.V. Rylov, “Novel architecture for superconducting flux-quantizing A/D converters,” Extended Abstracts of ISEC'93, Boulder, Colorado, USA, pp. 112-113, 1993. [2] S.V. Rylov and R.P. Robertazzi, “Superconducting high-resolution A/D converter based on phase modulation and multi-channel timing arbitration,” IEEE Trans. on Appl. Supercond., vol. 5, pp. 2260-2263, June 1995. [3] S.V. Rylov, L. A. Bunz, D. V. Gaidarenko, M. A. Fisher, R. P. Robertazzi, and O. A. Mukhanov, “High resolution ADC system,” IEEE Trans. Applied Superconductivity, vol. 7, pp. 2649-2652, Jun. 1997. [4] V.K. Semenov, Yu.A. Polyakov, and A. Ryzhikh, “Decimation filters based on RSFQ logic/memory cells”, In: Extended Abstracts of ISEC’97, Berlin, Germany, pp. 344-346, June 1997 [5] Bob Walden, Hughes Research Labs, walden@hrl.com The authors would like to thank O.A. Mukhanov and K.K. Likharev for useful discussions, Yu.A. Polyakov for help in testing and HYPRES fabrication team for making the ADC chips.
milstar: TRW continues the BMDO-funded program for the development of infrared (IR) focal plane array (FPA) imaging signal processing circuits, built in NbN and operating at 10 K. The BMDO project is part of the organization's effort to develop an integrated high-performance sensor with higher sensitivity for missile surveillance by developing and integrating high-performance superconducting ADCs and focal plane arrays. An ADC chip and digital signal processing chip were mounted on a 1.25 inch multi-chip module (MCM) with high bandwidth, low impedance interconnect (s. Fig. 15). The populated MCM is designed to be installed into a module housing for operation with the cryogenic IR FPA. A 12-bit NbN SFQ counting ADC, previously used in a single chip version of the IR focal plane array sensor test system, was now implemented in an improved NbN process which includes a ground plane. Considerable attention has been focused on reducing parasitic inductance to compensate for the high characteristic inductance of the NbN films. These design improvements increase operating margins and circuit yield and make the ADC more robust in the presence of external system noise. Data from a bit-serial subtraction circuit to be used for pixel-by-pixel background subtraction were also presented. The simultaneous high performance and ultra low power dissipation of superconducting circuits enables a long wavelength IR focal plane array sensor architecture featuring A/D conversion and digital signal processing in the cryogenic space very near, or on the focal plane. Sensors designed to detect long wavelength IR radiation (~ 25 µm) must operate at temperatures below 15 K in order to have low enough detector thermal noise. This requirement for cryogenic operation means an existing long wavelength sensor system can accommodate NbN superconducting circuits operating at 10 K without requiring a major system redesign. Performing A/D conversion followed by digital signal processing to enhance the signal-to-noise ratio and reduce the total data rate results in significant system-level payoff. TRW previously operated a 10 K, 12-bit, 2 MSps NbN ADC as part of a long wavelength IR focal plane array sensor demonstration (ISEC’97). In that demonstration, a 128 x128 long wavelength IR focal plane array was read out at 100 frames per second, producing IR images of room temperature objects against a cooled background, with all the data converted by a single NbN ADC dissipating 0.3 mW. The next step in the technology development is to demonstrate a system in which the first of the appropriate digital signal processing (DSP) functions is implemented in NbN circuitry and integrated with the ADC in the 10 K package. The circuit and packaging results reported at ASC’98 represent significant progress toward that goal. http://wwwifp.fzk.de/ISAS/Hottline/jun99/ADC.htm Northorp Grumman presented at ASC’98 sigma-delta architectures using large (>100) oversampling ratios to give signal-to-noise ratios of greater than 100 dB in simulation. Three distinct designs, using two distinct mechanisms for feedback were presented. All of the designs use only shunted junctions, and are therefore compatible with HTS SNS junctions of moderate IcRN products (~ 300 µV). The delta-sigma (D -S ) architecture allows for high dynamic range at large oversampling ratios. By adding feedback loops to the modulator, the dynamic range for a given oversampling ratio can be increased. Northorp Grumman chose to design two-loop modulators because of their intrinsic stability and ability to meet future radar specifications with a minimum of Josephson junctions. Three different two-loop modulators were described, each different in its feedback mechanism. One is based upon the concept of quantized integer feedback and three use "feedforward" signal for the second loop of the modulator. Each modulator is capable of operating at 10 GHz clock rates, necessary for the high dynamic range (> 100 dB SNR) needed for future naval and airborne ADCs.
milstar: a massively interleaved ADC 1. clock jitter management issue 2. neobxodimo imet w ADC a.offset adjust b.gain adjust c.apperture delay fine adjust http://www.atmel.com/journal/documents/issue6/Pg43_48_CodePatch.pdf
milstar: srawnitelnij anali po cenam ot razrjadnosti TI ADS5485 16 bit ,200 msps.SINAD 73.7db,ENOB-11.95,SFDR -87db ,129 $ ADS5474 14 bit,400 msps ,SINAD 68.9 db,ENOB -11.2 ,SFDR -86 gb ,200.65$ ADS5400 12 bit,1000 msps,SINDA-58 db,ENOB-9.3 ,SFDR -75 db,775$ T.e. skorost oceniwaetsja wische chem razrjadnost w neskolko raz ******************************************************** http://focus.ti.com/lit/ds/symlink/ads5400.pdf
milstar: http://www.astro.caltech.edu/USNC-URSI-J/Boulder%202009%20presentations/Tuesday%20AM%20J3/HawkinsSlides.pdf http://www.e2v.com/assets/media/files/documents/broadband-data-converters/doc0964C.pdf
milstar: http://www.youtube.com/watch?v=rznRrkPaeEg
milstar: in a flash ADC the number of comparators increases by a factor of 2 for every extra bit of resolution; simultaneously, each comparator must be twice as accurate ######################################################################################################### Flash/ili paralelnij) Max109 2.2 gigasamples ,8 bit ,256 comparators ,6.8 watt wozmozno interleaving ( 2- 4 ?)
milstar: powtor High resolution is particularly important in applications like imaging radar that must discern small objects close by ######################################################################### large objects, or in signals intelligence that must be able to characterize even the faintest radio signals in the presence of many other signals and electronic noise. ############################ Noise and distortion rejection is measured in two ways. The first is spurious noise dynamic range (SNDR), and the second is signal to noise ratio (SNR), both of which are measured in decibels, or dB. The higher the dB level of these two measurements, the better the A/D or D/A is at detecting and characterizing weak signals that may be important. Strong noise and distortion rejection is particularly important for applications like signals intelligence, radio communications, or sophisticated radar jammers. he larger the application, the more the designer concentrates on pure A/D and D/A converter performance, rather ########################################################################### than on device size and power consumption says Pam Aparo, ######################################### marketing manager for device maker Analog Devices High-Speed ADC Products segment in Greensboro, N.C. "Most of the requirements we get break down into 'the sky's the limit' in the performance and power that our users need," she says. "A ground-based radar is not concerned about power; they want all the performance they can get. ####################################################################### With missiles and communications and things people have to carry, it has to be a lightweight system, so we have to get the size and power down." ##################### No A/D or D/A converter -- at least not yet -- can be all things to all people. One rule of thumb is the faster the ######################################################################### device, the lower its resolution and noise rejection. On the other hand, the devices with the finest resolution and noise ########################################################################## rejection typically are not the fastest devices. It all depends on the application and the designer's needs. ###################################################################### One kind of radar jammer, for example, might have a high priority on speed, at the expense of resolution. ###################################################################### Above all, this system may need to detect radar signals quickly so it wastes no time in overwhelming the enemy ########################################################################### signal with jamming energy. In this application, it is not so important to characterize the radar signal with fine ####################################################################### resolution as it is to detect the radar signal quickly and jam it. ######################################## Signals intelligence and radio communications, on the other hand, put a priority on high resolution to detect and ########################################################################## classify weak signals of interest -- particularly when the desired signals are alongside strong signals or strong sources of noise. ######## A/D converter manufacturers like National Semiconductor in Santa Clara, Calif., Intersil, and others are pursuing interleaving technology, while others around the industry do not give this design approach much credence. ###################################################################### "People have tried ganging A/Ds together," says Rodger Hosking, vice president of signals intelligence and software defined radio processing specialist Pentek Inc. in Upper Saddle River, N.J. "In practice it is very difficult, and almost never works very well."
milstar: Providers of analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) Analog Devices Inc. Norwood, Mass. 781-329-4700 www.analog.com Atmel Corp. San Jose, Calif. 408-441-0311 www.atmel.com Austin Semiconductor Inc. (ASI) Austin, Texas 512-339-1188 www.austinsemiconductor.com Cirrus Logic Inc. Austin, Texas 512-851-4000 www.cirrus.com e2v Chelmsford, England +44 (0)1245 493493 www.e2v.com Hypres Inc. Elmsford, N.Y. 914-592-1190 www.hypres.com Intersil Corp. Milpitas, Calif. 408-432-8888 www.intersil.com Linear Technology Corp. Milpitas, Calif. 408-432-1900 www.linear.com Maxim Integrated Products Inc. Sunnyvale, Calif. 408-737-7600 www.maxim-ic.com Maxwell Technologies Inc. San Diego, Calif. 858-503-3300 www.maxwell.com Microchip Technology Inc. Chandler, Ariz. 480-792-7200 www.microchip.com National Semiconductor Santa Clara, Calif. 408-721-5000 www.national.com QP Semiconductor Santa Clara, Calif. 408-737-0992 www.qpsemi.com Schoenduve Corp. San Jose, Calif. 650-962-8330 www.schoenduve.com STMicroelectronics Inc. Geneva, Switzerland +41 22 929 29 29 www.st.com SUMMIT Microelectronics Inc. Sunnyvale, Calif. 408-523-1000 www.summitmicro.com QualCore Logic Inc. Sunnyvale, Calif. 408-541-0730 www.qualcorelogic.com Rohm Semiconductor USA LLC San Diego, Calif. 858-625-3630 www.rohmelectronics.com Teledyne Scientific & Imaging LLC Thousand Oaks, Calif. 805-373-4545 www.teledyne-si.com Texas Instruments - Semiconductor Products Dallas, Texas 972-644-5580 www.ti.com Universal Semiconductor Inc. San Jose, Calif. 408-436-1906 www.universalsemiconductor.com Wavefront Semiconductor Cumberland, R.I. 401-658-3670 www.wavefrontsemi.com Wolfson Microelectronics Plc. Edinburgh, Scotland +44 (0) 131 272 7000 www.wolfsonmicro.com
milstar: powtor ot National about 3.6 gsps/12 bit interleaved in one chip Of course, to get these very high speeds you can time interleave multiple converters. One competitor has interleaved four 550 MSPS ADCs to get to 2 GSPS but this is quite a complex solution. It is difficult to design this at board level and it consumes quite a lot of power. In half the board area (which has cost implications) we can achieve almost twice the speed and the power consumption is half. And we have one chip compared to four so we offer a lot of advantages for designers. http://www.analog-eetimes.com/en/12-bit-adc-paves-the-way-for-new-generation-of-software-defined-radio-solutions.html?cmp_id=7&news_id=222900778&vID=11 An example is with the LIDAR laser range measurement systems which are used in many industrial and military applications. With laser measurement systems the accuracy of these is determined by the sampling speed of the ADC. If you can increase the speed by three times then you have three times more accuracy of the distance measurement. You are enabling highly accurate measurement equipment by relating it s performance to the sample speed of the ADC. Sample rate is key and we are going up to sample rates of 3 GSPS which is miles ahead of what's available today. Today you can only do 1 GSPS at 12-bits now we have pushed that the whole way up to 3.6 GSPS which would have ########################################################################### been thought impossible a few years ago. This allows you to do a bandwidth instantaneously at 1.8 GHz which is huge ############################################################################ and combining that with 12-bit dynamic range means you grab the attention of the communications market because ########################################################################### with this much resolution you can do really useful work in communications systems, in military radar systems and in high-end test equipment. #################### There is also the fact you can simplify architectures by eliminating and reducing components, reducing board area. There are also a lot less thermal problems and board design complexity. There is also the benefit that it offers low power consumption because this is a pure CMOS technology. About Paul McCormack Paul McCormack is the Marketing Manager for National Semiconductor's High-speed product group and is based at the company's European Headquarters in Furstenfeldbruck near Munich. In addition to the ADC12D1800, National is also introducing two other members of its ultra high-speed ADC family: the ADC12D1600 with sampling speed up to 3.2 GSPS and the ADC12D1000 with performance up to 2.0 GSPS. All three PowerWise ADCs target wideband SDRs including radar, communications, multi-channel set-top box (STB), signal intelligence, and light detecting and ranging (LIDAR) applications. Key Features of the ADC12D1x00 12-bit, Ultra High-Speed ADCs, include: National’s 12-bit ADCs are supplied in a leaded or lead-free, 292-ball, thermally enhanced BGA package, and are pin-compatible with the ADC10D1000 and ADC10D1500 ADCs. The 12-bit ADCs run off a 1.9 V single supply and consist of two channels that can operate interleaved or as independent channels. They include circuitry for multi-chip synchronization, programmable gain and offset adjustment per channel. The internal track-and-hold amplifier and extended self-calibration scheme enable a flat response of all dynamic parameters for input frequencies exceeding 2 GHz, while providing a low 10-18 code error rate. The ADC12D1800 provides sampling rates up to 3.6 GSPS, or dual-channel rates up to 1.8 GSPS. In addition to excellent noise floor, NPR and IMD performance, the ADC12D1800 offers 57.8 dB SNR, 67 dBc SFDR and 9.2 ENOB at 125 MHz. The energy-efficient design consumes only 2.05 W per channel. The ADC12D1600 delivers single-channel sampling rates up to 3.2 GSPS, or dual-channel rates up to 1.6 GSPS. It features a -147.5 dBm per Hz noise floor, 52 dB NPR and -63 dBFS IMD. The ADC12D1600 consumes 1.9W per channel and offers 58.6 dB SNR, 68 dBc SFDR and 9.3 ENOB at 125 MHz. The ADC12D1000 provides single-channel sampling rates up to 2.0 GSPS, or dual-channel rates up to 1.0 GSPS. The device features a -147.5 dBm per Hz noise floor, 52 dB NPR and -66 dBFS IMD. The ADC12D1000 consumes 1.7 W per channel and offers 59.1 dB SNR, 70.5 dBc SFDR and 9.5 ENOB at 125 MHz. A space-qualified version of the ADC12D1x00 will be supplied in a hermetic 376 column, ceramic column grid array ########################################################################## (CCGA) package that meets radiation levels of 120 MeV for single event latch-up and a total ionizing dose of 100 Krads (Si). ############### The device is pin-compatible with the ADC10D1000QML 10-bit ADC. Availability and Pricing All three ADCs are sampling now, with production quantities available in the third quarter of 2010. Non-flight prototyping units and evaluation boards in the CCGA package will be available in the third quarter of 2010. Related links: ADC12D1800 ADC12D1600 ADC12D1000
milstar: Texas instruments 4*14 protiv 1*14 bit Fs=1.6 GS/s, SFDR=88 dBc (chastota Fi ?), ENOB=11.1 bits. HD2 -90 db ,HD3- 93 db http://spdevices.com/index.php/products2/adx4-evm-1600-14 ####################################### 1 *ADS5474 SFDR 70 mgz -86 db 230 mgz -80 db 351 mgz -76 db 451 mgz -71 db 651 mgz -60 db 751 mgz -55 db 999 mgz -46 db HD2 Second-harmonic fIN = 30 MHz 89 fIN = 70 MHz 87 fIN = 130 MHz 90 fIN = 230 MHz 84 fIN = 351 MHz 76 dBc fIN = 451 MHz 71 fIN = 651 MHz 74 fIN = 751 MHz 70 fIN = 999 MHz 55 SINAD Signal-to-noise and distortion fIN = 30 MHz 69.2 fIN = 70 MHz 67 68.9 fIN = 130 MHz 68.5 fIN = 230 MHz 65.5 68.2 fIN = 351 MHz 67.3 dBc fIN = 451 MHz 64.8 fIN = 651 MHz 58.5 fIN = 751 MHz 54 fIN = 999 MHz 45.4 http://focus.ti.com/lit/ds/symlink/ads5474.pdf Neyasno na kakoj Fin priwedeni dannie dlja 4 interleaved po SFDR,ENOB 1600 msps eto 800 mgz
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