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Operazionnie ysiliteli ,ZAP/AZP & (продолжение)
milstar: 1941: First (vacuum tube) op-amp An op-amp, defined as a general-purpose, DC-coupled, high gain, inverting feedback amplifier, is first found in US Patent 2,401,779 "Summing Amplifier" filed by Karl D. Swartzel Jr. of Bell labs in 1941. This design used three vacuum tubes to achieve a gain of 90dB and operated on voltage rails of ±350V. ###################################################### It had a single inverting input rather than differential inverting and non-inverting inputs, as are common in today's op-amps. Throughout World War II, Swartzel's design proved its value by being liberally used in the M9 artillery director designed at Bell Labs. ######################################################################### This artillery director worked with the SCR584 radar system to achieve extraordinary hit rates (near 90%) that ####################################################################### would not have been possible otherwise.[3] ########################### http://en.wikipedia.org/wiki/Operational_amplifier
milstar: 8B. 3 A GENERIC RADAR ... within the FPGA, a wide range of radar intermediate ... down converter as well as any oversampling that takes place within the radar ... http://ams.confex.com/ams/pdfpapers/123642.pdf IF processor -wiigrisch dopolnitelno 14 db k ADC 71 db PDF] Digital IF receiver - capabilities, tests and evaluation Adobe PDF - View as html ... analog circuits to down convert the signal from intermediate ... incorporation into the WSR-88D RRDA (Research Radar ... The oversampling mode plot of the dynamic range measurement ... http://ams.confex.com/ams/pdfpapers/64211.pdf kombinazija sampling i zifrowoj filtrazii -dinamicheskij diapazon 90 db s 14 bit ADC ,kotorij imeet SFDR tolko 71 db
milstar: Summer 2010 Vol. 19, No. 2 Model 71621 3 kanala s ADS5485 200 msps /16 bit TI IF 120-160 mgz To conserve resources, we will try an undersampling solution for digitizing the input signals. If we sample at 200 MHz, the signals of interest will fold as shown in Figure 7: the 120 MHz lower band edge translates to 80 MHz; the 140 MHz center frequency translates to 60 MHz; and the upper band edge translates to 40 MHz. http://www.pentek.com/pipeline/19_2/Radar.cfm http://www.pentek.com/products/Detail.cfm?Model=71621 Monopulse Radar Signal Processing This is a real-life example of the signal processing involved with a typical monopulse radar application. As shown in Figure 3, the system uses a multi-element antenna where the received signals consist of three types: Azimuth, Elevation and the sum of these two. The signals to be digitized and processed are as follows: * Azimuth difference or ΔA which is equal to A1 – A2 * Elevation difference or ΔE which is equal to E1 – E2 * Sum Channel Σ which is equal to the sum of A1 + A2 + E1 + E2 * The phase shift between Σ and ΔE determines the elevation of the target * The phase shift between Σ and ΔA determines the azimuth of the target * The IF center frequency of these signals is 140 MHz and the IF bandwidth is 40 MHz * This signal processing requires three channels of A/D converters Summary The Pentek Model 71621 Transceiver XMC module is a complete radar signal generation, timing and acquisition subsystem. It has the three A/Ds required for monopulse radar and standard on-board support for signal generation and acquisition timing. Radar data acquisition is facilitated by the 200 MHz, 16-bit A/Ds which capture the 140 MHz IF signals with 40 MHz bandwidth. Wideband DDC IP cores convert the IF signals down to baseband. The A/D input controller engine uses a simple parameter table that creates programmable delays, acquisition record lengths and complex acquisition scenarios. Radar waveform generation uses a D/A controller engine with a simple parameter table. It creates multiple waveforms with programmable delays and lengths. The wideband DUC upconverts the digital baseband waveform to 140 MHz IF and the 400 MHz, 16-bit D/A delivers 140 MHz IF signal with 40 MHz bandwidth.
milstar: http://www.analog.com/static/imported-files/data_sheets/AD9467.pdf “This is a breakthrough device. It’s pushing the state of art,” Jon Hall, ADI’s strategic marketing and applications manager for high-speed converters, said in an interview. The performance and power gains came thanks to a process shift rather than a process shrink. --------------------------------------------------------- The device is fabricated on .18 silicon germanium BiCMOS, ######################################################### where similar earlier devices were in CMOS. http://www.eetimes.com/electronics-products/electronic-product-reviews/analog-products/4208854/Analog-Devices-offers-16-bit-ADC-at-250-MSPS Togda mozno predpolozit wozmoznost sodanija 18 bit 100 msps s rasseiwaemoj moschnostju 10 watt i SFDR 107 db na Fin 70 mgz(standartnaja 2 pch w satcom) ################################ Product Review Analog Devices offers 16-bit ADC at 250 MSPS Brian Fuller 9/27/2010 6:57 PM EDT Comment Jon.Hall 10/21/2010 5:43 PM EDT The latency of the AD9467 is determined by the actual pipeline architecture. The ... GREAT-Terry 10/11/2010 8:15 AM EDT It is said to be a pipeline ADC. From the datasheet, the latency is 16 cycles. ... More Comments > Claiming a breakthrough in speed for the high-performance segment, Analog Devices today announced the AD9647 16-bit A/D converter operating at 250 MSPS (mega samples per second). The device, intended to drive the company’s converter presence broader and deeper into military, industrial and wireless applications, is said to have a sampling rate that is 25 percent faster than competitive devices. It uses 35 percent less power, at 1.32W total power dissipation including drivers, than competing devices, the company claimed. Key features: * 1.8 V and 3.3 V supply operation * 16-bit resolution with high signal bandwidths up to 300 MHz * On-chip IF (intermediate frequency) sampling circuit and buffered analog inputs * High dynamic range over broad signal bandwidth enables software-defined radios for use with multiple standards, such as LTE/W-CDMA, MC-GSM (class 1) and CDMA. * 75.5 dBFS SNR to 170 MHz at 250 MSPS @ 2.5 V p-p FS * 74 dBFS SNR to 170 MHz at 250 MSPS @ 2.0 V p-p FS * 90 dBFS SFDR to 300 MHz at 250 MSPS (@ −1 dBFS) at 2.5 V p-p FS * 95 dBFS SFDR to 170 MHz at 250 MSPS (@ −1 dBFS) at 2.0 V p-p FS * 100 dBFS SFDR at 100 MHz at 160 MSPS (@ −1 dBFS) * 60 fs rms Jitter “This is a breakthrough device. It’s pushing the state of art,” Jon Hall, ADI’s strategic marketing and applications manager for high-speed converters, said in an interview. The performance and power gains came thanks to a process shift rather than a process shrink. The device is fabricated on .18 silicon germanium BiCMOS, where similar earlier devices were in CMOS. http://www.eetimes.com/electronics-products/electronic-product-reviews/analog-products/4208854/Analog-Devices-offers-16-bit-ADC-at-250-MSPS --
milstar: http://www.analog.com/en/press-release/10_26_09_ADI_Expands_Low-Power_Data_Converter_Port/press.html Wisokoskorostnie 16 bit ADC s nizkoj potr .moschnsotju( 0.1 watta ) ...dlja nosimix radiostanzij http://www.analog.com/en/press-release/10_26_09_ADI_Expands_Low-Power_Data_Converter_Port/press.html ANALOG DEVICES EXPANDS LOW-POWER DATA CONVERTER PORTFOLIO WITH 26 HIGH-SPEED ADCS - New 16-bit, low-power, high-speed ADCs include three industry technology firsts in error correction, speed, and size. Norwood, MA (10/26/2009) - Analog Devices, Inc. (NYSE: ADI), the global leader in data-conversion technology for signal processing applications, expanded its low-power data converter portfolio with 26 ADCs (analog-to-digital converters) for effective high-performance, power-efficient communications, portable device, instrumentation and healthcare applications. The offering includes three data converter technology industry firsts for 16-bit ADCs: ADI’s AD9269, the industry’s first 16-bit 80 MSPS low-power, dual ADC with quadrature-error correction (QEC) ADI’s AD9265, the industry’s first single-channel, 16-bit low-power ADC spanning 80 to 125 MSPS (megasamples per second) ADI’s AD9266, the industry’s smallest, single-channel 16-bit low-power ADC spanning 20 to 80 MSPS These new ADC products provide designers a flexible, future-proof platform to differentiate their systems without changing the core design by migrating either resolution or bandwidth support by means of space efficient pin compatible families. In addition, the new ADCs’ energy efficiencies provide significant power consumption improvement without impacting system-level performance. In addition to the AD9269, AD9265 and AD9266 flagship converters and their various speed grades, ADI introduced today 23 single-channel low-power ADCs, bringing the number of low power data converters ADI has brought to market in the last 180 days to 44*. The power consumption savings across these ADCs is as high as 87% compared to equivalent competitive offerings operating comparable ADC functions. Industry First: Sub 100 mW/Channel, Low-Power, Dual-Channel ADC Spans 20 to 80 MSPS The dual-channel AD9269 16-bit low-power ADC consumes 93 mW per channel, which is 6.5 times lower than competing devices. The AD9269 is a monolithic, dual-channel 16-bit, 20/40/65/80 MSPS ADC, featuring a high performance sample-and-hold circuit and on-chip voltage reference. It’s also the industry’s first 16-bit ADC family to include a QEC and DC offset digital processing block. These blocks dynamically minimize the errors produced in an in-phase/quadrature (I/Q) complex signal receiver system. By using the QEC block, system designers can relax component matching requirements by reducing gain and phase errors due to component mismatches. The net result can also enable a more robust receiver design. In addition, the DC-offset algorithm minimizes offsets commonly found in DC-coupled applications. The product uses multistage differential pipeline architecture with output error correction logic to provide 16-bit accuracy at 80-MSPS data rates and guarantees no missing codes over the full operating temperature range. The ADC operates from a 1.8-V supply and contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital-test-pattern generation. Samples are available now with production quantities available in January, 2010. Industry First: Low-Power, Single-Channel 16-bit ADC Clocks at 125 MSPS The single-channel AD9265 low-power, 16-bit ADC was designed to support communications applications requiring low bill-of-material costs, small size, and flexibility. Consuming only 370 mW, this breakthrough in power consumption represents a 51 percent savings compared to competitive low-power solutions. The ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. The AD9265 features a wide bandwidth differential sample-and-hold analog input amplifier supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. A duty cycle stabilizer provides means to compensate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance. The ADC output data are either parallel 1.8 V CMOS or 1.8 V LVDS (DDR). Flexible power-down options allow significant power savings, when desired. Programming for setup and control are accomplished using a 3-bit SPI-compatible serial interface. Production quantities are available now. Industry First: Smallest 16-bit Low-power, Single-channel ADC Spans 20 to 80 MSPS The single-channel AD9266 16-bit, low-power ADC is available in a small 5 mm x 5 mm package, and the pin-out supports resolutions from 10 to 16 bits. The low-power, multistage ADC core is based on a proprietary, high-performance, sample-and-hold circuit and on-chip voltage reference. The product uses a differential-pipeline architecture with output-error-correction logic to provide 16-bit accuracy at 80 MSPS data rates and guarantees no missing codes over the full operating temperature range. The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the SPI. A differential clock input controls all internal conversion cycles. An optional DCS compensates for wide variations in the clock duty cycle while maintaining excellent overall ADC performance. The digital output data are presented in offset binary, Gray code, or twos complement formats at double-data-rate low-voltage CMOS levels. A data output clock (DCO) is provided to ensure proper latch timing with receiving logic. Samples are available now with production quantities available in January, 2010. Pricing, Tools and Complementary Products
milstar: primer SDR modifikazija wsr-88d- If /pch-57-62.5 mgz ,14 bit ADC /Lockheed -Martin 3 ghz radar s 9 metrow antennoj http://www.qsl.net/n9zia/pdf/wsr-88d.pdf http://www.roc.noaa.gov/WSR88D/About.aspx There are 159 operational NEXRAD radar ... Generic radar processor design using software defined radio ---------------------------------------------------------------- 8B. 3 A GENERIC RADAR ... within the FPGA, a wide range of radar intermediate ... down converter as well as any oversampling that takes place within the radar ... http://ams.confex.com/ams/pdfpapers/123642.pdf s IF 62.5 mgz ... T.e. eto ne prjamaja konversija signal s antenni w ADC ----------------------------------------------------------- PDF] Digital IF receiver - capabilities, tests and evaluation Adobe PDF - View as html ... analog circuits to down convert the signal from intermediate ... incorporation into the WSR-88D RRDA (Research Radar ... The oversampling mode plot of the dynamic range measurement ... http://ams.confex.com/ams/pdfpapers/64211.pdf kombinazija sampling i zifrowoj filtrazii -dinamicheskij diapazon 90 db s 14 bit ADC ,kotorij imeet SFDR tolko 71 db posle modifikazii na pdf linkax wische s 14 bit ADC http://www.qsl.net/n9zia/pdf/wsr-88d.pdf Chastota 2.7 ghz -3 ghz Nesuschaja pch -60 mgz polosa -0.8 mgz dinamicheskij diapazon -95 db Na sxemax 2008 goda nize s 16 -bit ADC 105 db ------------------------------------------------- http://highfrequencyelectronics.com/Archives/Sep08/HFE0908_S_Crean.pdf http://highfrequencyelectronics.com/Archives/Nov08/1108_Friedman.pdf
milstar: A great deal of the technological groundwork for this process was established during 1971. By 1972, fabrication of the first reflective-array compressor (RAC) was initiated; this device is illustrated in Figure 2. The first RAC device was a linear-FM filter with a 50-MHz bandwidth (on a 200-MHz carrier) matched to a 30-μsec-long waveform [16–18]. This arrangement yielded a time-bandwidth product of 1500, more than an order of magnitude greater than that achieved by interdigital-electrode SAW devices [19]. The response was remarkably precise; the phase deviation from an ideal linear-FM response was only about 3° root mean square (rms). Pairs of matched RACs were used in pulse-compression tests in which the first device functioned as a pulse expander and the second as a pulse compressor. The compressed pulsewidths and sidelobe levels were near ideal. Armed with these encouraging results, researchers took the next step by developing RAC devices for specific Lincoln Laboratory radars. http://www.ll.mit.edu/publications/journal/pdf/vol12_no2/12_2radarsignalprocessing.pdf FIGURE 2. A phase-compensated reflective-array compressor, or RAC. The input transducer converts an electrical signal into a surface acoustic wave (SAW) that propagates along the surface of the crystal. The grating etched into the crystal reflects the wave at a position determined by the input frequency and the local spacing of the grooves in the grating. High frequencies reflect close to the input transducer, while low frequencies reflect at the far end of the grating. A second reflection sends the SAW to the output transducer, where it is converted back into an electrical signal. The desired delay versus frequency is set by the geometry of the device. Deviations from the desired response can be trimmed out by a metal film of varying width deposited on the device. The wide bandwidth yielded a range resolution that could resolve individual scatterers on reentering warhead-like objects. This waveform was normally processed with the STRETCH technique, which is a clever time-bandwidth exchange process developed by the Airborne Instrument Laboratory [21, 22].
milstar: The ARPA-Lincoln C-band Observables Radar, or ALCOR [20], on Roi-Namur, Kwajalein Atoll, Marshall Islands, had a wideband (512 MHz) 10-μseclong linear-FM transmitted-pulse waveform (see the article entitled “Wideband Radar for Ballistic Missile Defense and Range-Doppler Imaging of Satellites,” by William W. Camp et al., in this issue) The return signal is mixed with a linear-FM chirp and the low-frequency sideband is Fourier transformed to yield range information. For a variety of reasons, the output bandwidth and consequently the range window were limited. For example, the ALCOR STRETCH processor yielded only a thirty-meter data window. *********************************** Therefore, examination of a number of reentry objects, or the long ionized trails or wakes behind some objects, required a sequence of transmissions.
milstar: 16-битные АЦП-приемники на основе технологии SiP — без лицензии на импорт Действующие экспортные ограничения в области высоких технологий, в том числе на быстродействующие АЦП, серьезно ограничивают российских производителей коммуникационного, измерительного и другого оборудования, в котором могут использоваться подобные АЦП. И хотя лицензию на поставки таких компонентов получить можно, ограничения все равно препятствуют широкому внедрению скоростных АЦП и не дают нашим разработчикам набрать опыт использования устройств такого класса, снижая конкурентоспособность отечественных разработок http://www.russianelectronics.ru/leader-r/review/2190/doc/48505/ 1. Pochemu USA dolzni postawljat AZP potenzialnomu protiwniku neponjatno 2. Pochemu Rossija dolzna zawisit ot COCOM ,toze Neobxodimo razrabotat swoi AZP .... 3 Opit est ,swoi AZP bili toze . W 1994 posle 3 preobrazownij chastoti 35 ghz/2000 mgz polosa MMW radar ispolzowal 10 bit AZP s 20 msps na 2.5-7.5 mgz ------------------------------------------------------------ Toze primerno bilo w Don -2N http://www.rti-mints.ru/pro.htm В РЛС реализована полностью цифровая обработка сигналов (ЦОС). Инициатором и организатором работ по внедрению ЦОС в РЛС ПРО “Дон-2Н” являлся ее главный конструктор. За создание РЛС “Дон-2Н” ее главный конструктор В.К.Слока в 1996 г. удостоен высокого звания Героя Российской Федерации Po publichnoj informazii *********************** K sozaleniju razrabotkoj 16 bitnix AZP 200-300 msps weduschie rossijskie centri ********************************************************************** NTZ Modul - http://www.module.ru/ FGUP Progress - http://mri-progress.ru/ sejtchas zanimatsja ne budut *************************** Nesmotrja na nalichie y nix texnologii i processa 0.18 microna SiGE BiCMos ( AD9467 250 msps ,300 mgz sdelan na etoj texnologii) wozmoznie prichini -drugie idei ,celewoj rinok -meschanskaja massa , nabor reklamnix primitiwizmow - ----------------------------------------- sistema na kristalle SDR 1. Kniga chefa FGUP Progress http://mri-progress.ru/?p=92 Представляем вашему вниманию книгу серии “Мир электроники”, авторы Немудров В., Мартин Г. “Проектирование систем на кристалле”, издательство “Техносфера”, 2004 г. В книге рассмотрены различные аспекты проектирования и развития нового класса перспективной электронной элементной базы – “систем на кристалле” (system-on-chip – SoC). 2. Interviju chefa NTZ Modul http://www.electronics.ru/issue/2005/6/1 За DSP Л1879ВМ1 последовала система на кристалле (СнК) 1879ВМ3 - чип смешанной обработки, включающий два канала АЦП с быстродействием 600 мегавыборок в секунду и четыре 8-разрядных ЦАП по 300 Мвыборок/с, встроенное ОЗУ (2 Мбит), управляющий контроллер с VLIW-архитектурой (128-разрядные команды) и развитой шинной структурой. Вскоре должен последовать новый DSP-процессор 1879ВМ2. "Mochit w sortire" , "Prinuzdenie k miru" , "Informazionnie ydari" (nach.staba VKS), Nanotrubki , Sistema na kristalle i tak dalee... Maloverojatno ,chto dannie FGUP/kompanii zainteressowani razrabatiwat specializirowannij 16 -biz AZP dlya VPK http://www.youtube.com/watch?v=9cVqNT0grx8
milstar: ADC http://www.nu-trek.com/nu-trek/data-conversion.html/#Ultra%20Low%20Power%20ADCs Ultra Low Power Analog to Digital Converters (ADCs): Two ultra-low power 14-bit ADCs are under development. Power consumption is ~ 1/10 of commercial parts that are presently on the market. ADCs target imager applications. odno iz primenenij ADC wische http://www.nu-trek.com/nu-trek/rf-applications.html The device supports multichannel digital adaptive anti-jam signal processors providing wideband cancellation in excess of 50 dB. When combined with a GPS signal processor providing 70 dB A/J the RF ASIC will support GPS tracking with 120 dB Jamm/Signal. ################################################### The NTK-Ironman-01 is a complete dual-channel global positioning system (GPS) front-end down converter. This low power CMOS IC integrates a low-noise amplifier (LNA), image rejection mixer, automatic-gain-control amplifier (AGC), secondary mixer, and clock buffer. External IF, baseband filters, and ADCs enhance flexibility. The device ####################################################################### supports C/A, P(Y), and M codes. ################################ Government sponsors have included the: Missile Defense Agency (MDA) U.S. Air Force Department of Energy (DOE) Defense Threat Reduction Agency (DTRA) Defense Advanced Research Projects Agency (DARPA) U.S. Navy National Aeronautics and Space Administration (NASA) Key industrial partners included: Raytheon Ball Aerospace Honeywell SAIC Other Prime and 2nd Tier Defense Contractors http://www.nu-trek.com/nu-trek/aboutus.html
milstar: A Few Words About Intermodulation Dynamic Range (IMDDR) and Roofing Filters http://www.inrad.net/files/Pubs/About%20Roofing%20Filters.pdf The term “roofing” means that it protects the rest of the radio following it from out of the passband signals. --------------------------------------------------------------------------------------------------------------------------- Modern radios are two basic designs: radios with only ham bands use a first IF in the HF region, typically between 4 and 10 MHz, or radios that have their first IF in the VHF region, well above 30 MHz. The latter are usually called “Up Conversion” radios. Let’s examine some of the advantages of each. The Orion, K2, and Omni are like the first type. The Yaesu, Kenwood, and Icom radios are like the second. The first IF in the Orion is in the HF region. These filters are easy to make and have been available for many years. In the up conversion radios, the first IF is at VHF, somewhere in the 40 to 75 MHz region. ------------------- RADAR FPQ -6 Appolo programm IF -20 mgz ,polosa 1.6 mgz Sputnik kommunikazii 1 IF 1-1.15 ghz ,2 IF -70 mgz ,polosa 4-5 mgz (Misltar/AEHF 8.192 mbps) ------------------------------------------------------------------------------------------------------------------ rezim naibolschej boewoj ystojchiwosti Milstar-2/AEHF -75 bit/sek(polosa 75 herz primerno) ############################################ The ability of a radio to ignore strong signals near the tuned frequency is greatly enhanced by a roofing filter ####################################################################### . Ideally, the final desired selectivity should be in the first IF to protect the following high-gain stages from strong out-of-band signals. At the lower IFs it is possible to use filters as narrow as 250 Hz. ########################################### Roofing Filters and Dynamic Range Following the antenna connection, most radios have an LC bandpass filter. This filter is usually as wide as an amateur band or even wider. So, the first mixer may have tens or hundreds of signals at its input while you are trying to separate out one signal for copy. The ability of the first mixer to handle these signals without excessive intermodulation is a function of its circuit design. It does have a limit, above which there is intermodulation that becomes stronger than the noise floor of the radio. The difference between these two levels is known as the dynamic range. This characteristic is generally measured with just two signals of the same strength and some particular frequency spacing. For two signals within the operating band, this is called the third-order dynamic range. When the signal spacing is much greater than the roofing filter bandwidth, the dynamic range of the radio is determined by the first mixer and any other early stages.
milstar: http://www.electronics.ru/pdf/6_2003/04.pdf opisanie na russkom Подтверждением тому мо жет служить появление в июле 2003 года на сайте фирмы информа ции о создании нового, самого скоростного в мире 14разрядного АЦП ТС1410 с рекордным быстродействием – предельная частота дискретизации 240 МГц Пока же частотные показатели нового АЦП выглядят более скромно, хотя и занимают лидирующие в мире позиции. ###################################### В частно сти, для сигнала на частоту 5 МГц отношение сигналшум при дис кретизации с частотой 240 МГц достигает 71 дБ (полный коэффи циент гармоник – 87 дБс), монохроматического сигнала частоты 181 МГц – 70 дБ (полный коэффициент гармоник – 74 дБс) (рис.4). Yrowen 2003 goda ot Raytheon 14 bit 250 msps ,potr moschnsot 12-14 watt Esli w Rossii takoj sposbni sdelat ,to xoroscho Segodnjaschnij yrowen 250 msps ,16 bit 0.18 SiGE ,1.3 watta AD9467 ################################################# Eto open market(dlja wsex) . W specializirowannom voennom variante verojatno mozno ywelichit potr moschnsot w 10 raz(w S-500 eto nekriticno potr AZP 1.3 watta ili 13 watt ,kritichna skorost , tochnost ,din.diapazon) a chislo razrjadom do 18
milstar: Sowetskoe AZP ostanowilos na 1107pw6 10 razrjadnij s chastotoj wiborki bolee 40 megasample Takie werojatno stojat w Don-2N strech processing http://www.rti-mints.ru/pro.htm МРЛС “Дон-2Н” предназначена для обнаружения баллистических целей, их сопровождения, измерения координат, анализа состава сложных целей и наведения противоракет. Она способна одновременно сопровождать в автоматическом режиме до 100 элементов сложных баллистических целей (СБЦ) и одновременно наводить на них несколько десятков противоракет. За создание супер-РЛС “Дон-2Н” ее главный конструктор В.К.Слока в 1996 г. удостоен высокого звания Героя Российской Федерации и ему в Кремле Президентом страны была вручена “Золотая Звезда Герой России» nachalo 90 Lincoln laboratory MMW 35 ghz/13.7 metra antenna ispolzowal strech processing 20 megasample w polose 2.5-7.5 mgz
milstar: TC1410 TelASIC 14 bit ,240 msps 2003 god Input bandwitch - bolee 1000 mgz SNR -71.5 DB THD -85 db (Vin menee 240 mgz) SFDR -bolee 100 dbfs bez 2 i 3 harmoniki apperturnaja pogr - menee 60 femtosek max vx.signal 4 v(peak to peak) output -LVDS architecture -Multi-pass sub-ranging ,Integrated wideband sample & hold http://w2.cadence.com/whitepapers/wireless_solutions_sandiego_010605.pdf
milstar: http://rfdesign.com/mag/504rfdf1.pdf Fig.2 true software radio used single-cariier speed RF -to digital converter ############################################## to eliminate ll analog front-end components ############################### Korrektno ,no ADC s parametrami 24 bit ,120 db SFDR do 2.5 ghz w blizajschee wremja ne predwidetsja ---------------------------------------------------------------------------------------------------------------------------- Elecraft K3 -ljubitelkij priemnik s IF/pch - 8.15 mgz , 8 pole roofing filtr i DSP imeet dinamicheskij diapazon 140 db pri polose 400 gerz i signale pomexi ydallenim wsego na 2 kilogerza http://www.elecraft.com/ lutsche , chem true SDR Wincom na 16 bit ADC LTC2209 ############################################## http://winradio.com/home/g31ddc.htm
milstar: http://www.esicomputing.com/documents/HghSpdADG.pdf highspeedconverters techik -Tochka zrenija pentek
milstar: http://www.analog.com/static/imported-files/data_sheets/AD6650.pdf Blok pch slja GSM/Edge
milstar: http://focus.ti.com/lit/an/slyt388/slyt388.pdf analog application journal 4q 2010 analis clock jitter dlja 12 bitnogo i 16 bitnogo AZP
milstar: 12 bitnij ADC s SFDR typicaly -86dbfs na 105 mgz ,-80dbfs na 190 mgz http://www.intersil.com/data/fn/fn7604.pdf Y lutchix 16 bitnix AD9467 100 dbfs na 160 mgz Chastota 2 pch/IF -70 mgz w sputn i troposfernix kommunikazijax 1-2 pch/IF w radare 70-140 mgz
milstar: Key Features: Collaboration of Intersil and SP Devices Demonstrates 4-way Interleaving of Intersil 500MSPS ISLA112P50s Sample Rate: 2.0 GSPS Resolution: 12 Bits Interleave Correction Details SP Devices’s ADX4 provides real-time, digital, FPGA based digital interleave correction of four ISLA112P50s Performance SNR = 65.5 dBfs @ Fin = 190MHz, a 6dB improvement over current best standalone 2GSPS ADCs SFDR = 82 dBc @ Fin = 190MHz, a 13dB SFDR improvement over current best standalone 2GSPS ADCS http://www.intersil.com/converters/ADC_ref_design.asp
milstar: http://www.datasheetcatalog.com/datasheets_pdf/L/T/C/1/LTC1749.shtml LTC1749 12 bit 80 msps ADC dowolno starij (ochewidno bez bolschix problem mozet bit oswoeno proizwodstwo kopii w Rossii) SNR 71.7 -69 db SFDR 30 mgz - 87 dbc 70 mgz - 87 dbc 140 mgz - 84 dbc 250 mgz -80 dbc 350 mgz -74 dbc dlja srawnenija AD9467 ,SiGE BicMos 7-stage pipeline . presentazija 27.10.2010 16 bit ,250 msps http://www.analog.com/static/imported-files/data_sheets/AD9467.pdf SNR 74.6 -76.4 db SFDR 140 mgz -94/95 db 300 mgz -93/90 db pri -2db ot full scalle SFDR mozet bit 100 /100 db na 140-170 mgz 95 dBFS SFDR to 170 MHz at 250 MSPS (@ −1 dBFS) at 2.0 V p-p FS 100 dBFS SFDR at 100 MHz at 160 MSPS (@ −1 dBFS) http://www.analog.com/en/analog-to-digital-converters/ad-converters/ad9467/products/product.html?ref=PR_9-27-10_AD9467 i starij 12 bit i novij 16 bit mogut rabotat na 2 IF/Pch = 70 mgz signalom polosoj 8-10 mgz (pirmerno polosa milstar/aehf i troposfernoj swjazi) y 16 bitnogo budet preimuschestwo w dinamike na 13 db 100 dbc protiw 87 dbc ----------------------------------------------------------------------------------------------
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