Ôîðóì » Äèñêóññèè » Operazionnie ysiliteli ,ZAP/AZP & (ïðîäîëæåíèå) » Îòâåòèòü
Operazionnie ysiliteli ,ZAP/AZP & (ïðîäîëæåíèå)
milstar: 1941: First (vacuum tube) op-amp An op-amp, defined as a general-purpose, DC-coupled, high gain, inverting feedback amplifier, is first found in US Patent 2,401,779 "Summing Amplifier" filed by Karl D. Swartzel Jr. of Bell labs in 1941. This design used three vacuum tubes to achieve a gain of 90dB and operated on voltage rails of ±350V. ###################################################### It had a single inverting input rather than differential inverting and non-inverting inputs, as are common in today's op-amps. Throughout World War II, Swartzel's design proved its value by being liberally used in the M9 artillery director designed at Bell Labs. ######################################################################### This artillery director worked with the SCR584 radar system to achieve extraordinary hit rates (near 90%) that ####################################################################### would not have been possible otherwise.[3] ########################### http://en.wikipedia.org/wiki/Operational_amplifier
milstar: http://tscm.com/rcvr_sen.pdf Receiver sensivity /noise -114 dbm dlja polosi 1mgz pri komnatnoj temperature -174 db dlja polosi 1 gerz Minimum S/N 1.Dlja optinogo operatora z displeem 3-8 db 2.Awtodetekzija 10-14 db tipichnaja chustw . a. RWR -radar warning reciever -65 dbm (bolschaja polosa) b. Pulse radar -94dbm v. Missile seeker - 138 dbm idealnij primenik pri komnatnoj temperature 1 gerz -204 dbw ili -174 dbm 1khz -174 dbw ili -144 dbm 1mgz -144 dbw ili -114 dbm 1mgz -114 dbw ili -84 dbm tipichnij radar priemnik trebuet 3-10 db otlichit signal ot schumow i 10-20 db to tracj
milstar: conversija microvolt w dbm For the common situation where R=50, this simplifies to (9) dBm = 20 LOG Eµ - 107 Emju w mirovoltax esli priemnik imeet chustwitelnost 0.25 microvolt pri signal / k schumam i iskazenijam 12 db ############################################################### to 0.25 microvolta = -119 dbm ili 149 dbwatt i pri etom naprjazenii signala na wixode poleznij signal na 12 db(po moschnsoti 16 raz ,po napr 4 raza ) wische chem schum eto dlja polosi 1000 gerz A SINAD of 12-dB should provide a comfortable margin for copying voice communications. A skilled listener can probably copy voice signals which have a signal to noise ratio of much less than 12-dB. Very skilled listeners can copy voice signals which are at or below the noise level. http://continuouswave.com/whaler/reference/dBm.html http://continuouswave.com/whaler/reference/VHF.html http://continuouswave.com/ubb/Forum6/HTML/001847.html
milstar: klassischeskij priemnik predstawitelej wtoroj drewnejschej 80 godow Watkins Johnson WJ-8617B http://watkins-johnson.terryo.org/Documents/Manufacturers/WJ/Data%20sheets/WJ-8617B%20data%20sheet.pdf Schum -9.5 db ,Imagei If rejection -90 db ,chustwit dlja polosi 10 kgz -104 dbm ili dlja polosi 1 kgz -114 dbm
milstar: For a 1 Hz bandwidth and at 290 K: Pn = 1.38 * 10-23 * 290 * 1 Pn = 4 * 10-21 Watts Pn = -174 dBm For a 1 Hz bandwidth and at 1 K: Pn = 1.38 * 10-23 Watts Pn = -198 dBm za schet kriogenowogo oxlazdenija mozno wiigrat do 20 db ####################################### http://www.qsl.net/n9zia/receiver.html The wider the bandwidth, the greater the noise power and the higher the noise floor ######################################################## Consider a receiver that has a 1 MHz bandwidth and a 20 dB noise figure. If a S/N of 10 dB is desired, the sensitivity (S) is: S = -174 + 20 + 10log101,000,000 + 10 S = -84 dBm It can be seen from this that if a lower S/N is required, better receiver sensitivity is necessary. If a 0 dB S/N is used, the sensitivity would become -94 dBm. The -94 dBm figure is the level at which the signal power equals noise power in the receiver's bandwidth. If the bandwidth were reduced to 100 kHz while maintaining the same input signal level, the output S/N would be increased to 10 dB due to noise power reduction. ------- dlja RLS ispolzuemoj w Appolo proekt IF polosa bila 8 mgz ########################################## a S/N receiver bilo polutsche na 8db -10 t.e. w formule nize a. yxudschit na 8 db za schet raschirenija polosi s 1 mgz do 8 mgz b. ylutschit na 8 db za chet lutschej schumowoj xarakteristiki Consider a receiver that has a 1 MHz bandwidth and a 20 dB noise figure. If a S/N of 10 dB is desired, the sensitivity (S) is: S = -174 + 20 + 10log101,000,000 + 10 S = -84 dBm ############## A dinamicheskij diapazon bolee 120 db ... powtor dinamicheskij diapazon w stat'e Watkins -Johnson http://www.rfcafe.com/references/articles/wj-tech-notes/Rec_dyn_range2.pdf
milstar: 24 bit 4msps TI http://focus.ti.com/lit/ds/symlink/ads1675.pdf SFDR 120 db pri 4 msps i Fin 10 kghz THD -103 db na 10 kghz y 32 bitnogo THD -120 db pri 200 ksps http://www.esstech.com/PDF/SABRE32%20ADC%20PF%20081218.pdf
milstar: A 4 GSample/s 8b ADC in 0.35-um CMOS 0.35 microna texnologija est w Rossii bolee 10 let http://poulton.net/papers.public/2002isscc_10_1_tal.pdf Ken Poulton, Robert Neff, Art Muto, Wei Liu*, Andy Burstein**, Mehrdad Heshami*** Agilent Technologies, Palo Alto, CA *Agilent Technologies, Colorado Springs, CO ** now with Volterra Semiconductor, Fremont, CA ***now with Virata, Cupertino, CA Contact: Ken Poulton 650-485-8461 FAX: 650-485-3637 poulton@labs.agilent.com Presenter: Robert Neff 650-485-6220 FAX: 650-485-3637 neff@labs.agilent.com Figures are included here for reference; final figures are submitted as TIFF files. Abstract A 4-GSample/s, 8-bit ADC dissipates 4.6 W in 0.35-um CMOS. It creates 32
milstar: http://www.poulton.net/papers.public/2003isscc_18_1_pg.pdf 20 gigasamples/8 bit 0.18 microna As shown in Fig. 18.1.6, ADC accuracy reaches 6.5 effective bits at input frequencies up to 500MHz, mainly limited by thermal noise. ########################################### xuze chem y 10 bit not interleaved EV ,so skorostju 2.5 gigasample na 2500 mgz 7.7 bit It achieves 4.6 effective bits for a full-scale input at 6GHz, limited by jitter. Total jitter is 0.7ps rms, including external clock jitter, on-chip thermal jitter and residual timing misalignment. Misalignment after calibration is less than 0.4 ps rms. The ADC achieves a full-scale input signal bandwidth of 6.6GHz.
milstar: press release Nov. 4, 2010, 12:30 p.m. EDT Innovative 2GSPS Digitizer Reference Design Reduces Time to Market for Communications, Radar and Test Applications MILPITAS, CA, Nov 04, 2010 (MARKETWIRE via COMTEX) -- Intersil Corporation /quotes/comstock/15*!isil/quotes/nls/isil (ISIL 13.64, +0.38, +2.87%) today introduced the industry's most power-efficient 12-bit, 2 Gigasample/second (GSPS) digitizer reference design, developed to reduce design time for advanced communications, radar and test systems. Based on Intersil's ISLA112P50 500 Megasample/second (MSPS) converter, the new 2GSPS reference design meets industry requirements for increased sampling speeds, and eliminates artifacts typically caused by interleaved ADCs. Intersil collaborated with SP Devices to develop the new reference design. The Intersil reference design demonstrates detailed best practices in a known-good system, providing real-time, FPGA-based digital interleave correction of four ISLA112P50 devices. It features significant signal-to-noise and spurious-free dynamic range performance benefits compared with competing 2GSPS ADCs. The signal-to-noise ratio (SNR) is 65.5dB at a 190MHz input frequency, which represents an improvement of 6dB over competing solutions. Since SNR does not degrade significantly with higher input frequencies, this performance advantage is maintained over the entire bandwidth of the digitizer. Spurious free dynamic range (SFDR) is 81.7dBc at a 190MHz input frequency, an improvement of 13dBc. The reference design provides superior SFDR for input frequencies up to 500MHz. Four 12-Bit 500MSPS ISLA112P50 devices are interleaved to provide 2GSPS. Full power bandwidth is 750MHz, and ADC- and interleave-related power consumption is just 4.1W. For details on the SP Devices evaluation cards, please visit http://www.spdevices.com/index.php/products2/adx4-evm-2000-12. For information on the Intersil reference design, please visit http://www.intersil.com/converters/ADC_ref_design.asp. About the ISLA112P50 The ISLA112P50 is the latest in Intersil's expanding family of high performance, low-power ADCs. Developed for broadband communications, radar, light detection and ranging (LIDAR) and data acquisition systems, the new converter is built using Intersil's proprietary FemtoCharge(R) technology on a standard CMOS process. The converter's dynamic performance and specifications are optimal for targeted applications. Analog input bandwidth is 1.15GHz. Signal-to-noise ratio is 65.8dBFS and SFDR is 80dBc for an input frequency of 190MHz. The device incorporates nap/sleep modes, and digital output data is available in either LVDS or CMOS formats, increasing design flexibility. About Intersil Intersil Corporation is a leader in the design and manufacture of high-performance analog, mixed signal and power management semiconductors. The Company's products address some of the fastest growing markets within the communications, computing, consumer and industrial industries. For more information about Intersil or to find out how to become a member of our winning team, visit the Company's web site and career page at www.intersil.com. Intersil, the Intersil logo and FemtoCharge are trademarks or registered trademarks of Intersil Corporation. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. SOURCE: Intersil Copyright 2010 Marketwire, Inc., All rights reserved. http://www.intersil.com/converters/ADC_ref_design.asp Intersil 2GSPS Reference Design By interleaving Intersil's low power, high sample rate ADCs, it is possible to achieve a combination of ultra-high sample rate and very high dynamic range that is not available in today’s stand-alone ADCs. This reference design demonstrates the performance attainable by combining Intersil's ADC technology and SP Devices interleaving algorithms. In this design, 4 ISLA112P50 12-bit, 500 MSPS analog-to-digital converters are interleaved to sample at a rate of 2.0 GSPS. At this sampling rate, the reference design provides over 6dB more SNR and 13dB better SFDR than the best alternative stand-alone ADC.
milstar: Raznie priemi dlja ywleichenija SNR i SFDR ne wsegda prinosjat resultat 1. Averaging 2. Oversampling 3. Dithering 4. Interleaving When Oversampling and Averaging Will Work The effectiveness of oversampling and averaging depends on the characteristics of the dominant noise sources. The key requirement is that the noise can be modeled as white noise. Please see Appendix B for a discussion on the characteristics of noise that will benefit from oversampling techniques. Key points to consider are [2] [3]: • The noise must approximate white noise with uniform power spectral density over the frequency band of interest. • The noise amplitude must be sufficient to cause the input signal to change randomly from sample to sample by amounts comparable to at least the distance between two adjacent codes (i.e.,1 LSB - please see Equation 5 in Appendix A). • The input signal can be represented as a random variable that has equal probability of existing at any value between two adjacent ADC codes. Note: Oversampling and averaging techniques will not compensate for ADC integral non-linearity (INL). Noise that is correlated or cannot be modeled as white noise (such as noise in systems with feedback) will not benefit from oversampling techniques. ############# Additionally,if the quantization noise power is greater than that of natural white noise (e.g.,ther mal noise),then oversampling and averaging will not be effective. ######################## This is often the case in lower resolution ADC’s. The majority of applications using 12- bit ADC’s can benefit from oversampling and averaging. each additional required bit of resolution can be achieved via oversampling by a factor of four,and each additional bit will add approximately 6 db of SNR (Equation 3) at the cost of reduced throughput and increased CPU bandwidth. http://www.premier-electric.com/files/Cygnal/AppNotes/AN018.pdf If we are using the 12-bit on-chip ADC and wish to have the accuracy of a 16-bit ADC,we need an additional 4 bits of resolution. Four factors of four (using Equation 11) is 256. Thus,we need to oversample by a factor of 256 times the Nyquist rate. If the desired signal is band-limited to 60 Hz (fm=60 Hz),the n we must oversample oversample at 120 Hz * 256 = 30.7 kHz. We improve the effective resolution by improving the SNR in our frequency band of interest. Increasing the sampling rate,or OSR,lowers the noise floor in the signal band of interest (all frequencies less than 1/2 of fs). W kommunikazijax s wisokoj boewoj ystojschiwostju polosa mozet bit i 1 herz no y radara minimum 8 megaherz ######################
milstar: http://www.actel.com/documents/Improve_ADC_WP.pdf esche odin primer ...no eto wse dlja nizkix chastot ,ne dlja polosi 8 megaherz ,na nesuschej 30 mhz i 16 bit 250 msps aDC
milstar: Texas Instruments teorija i praktika dlja 14 bit 190 msps ADC ############################################ By using three ADCs instead of one, the SNR ideally improves by 4.8 dB, as derived below, which boosts the 14-bit ADC (SNR ∼74dB) to a 16-bit ADC level (SNR ∼79dB). he averaging technique reduces uncorrelated white noise, but has no effect on distortions inherent to the ADC design that might be common to all three ADCs. If, for example, the ADC creates a large third-order distortion product, it will show up in each ADC used and averaging won't reduce it. Therefore, averaging only improves SNR, but not spurious free dynamic ############################################################################# range (SFDR). ########### ywelichit SFDR mozno s pomoschju dithering - ....dobawleniaj schuma Zamer resultata ############ Measurements In order to verify the SNR gain, a board was designed containing three ADS5546 ADCs (14-bit, 190 Msps) and an FPGA that was used to perform a 3:1 averaging function. Using two or three standalone ADC evaluation modules (EVM) for this experiment usually doesn't work as well, because noise coupled into the cable assembly is correlated and, therefore, doesn't average out. ################# Furthermore, if the cables are not matched very well, skew between ADCs adds phase mismatch and further degrades the overall SNR. http://www.eetimes.com/design/automotive-design/4009960/Multiple-A-Ds-versus-a-single-one-pushing-high-speed-A-D-converter-SNR-beyond-the-state-of-the-art
milstar: w itoge poluchilos Table 1: Results of test; SNRJitter is converted to dB FS: SNR[dB FS]= SNR[dBc]+1 (at -1 dB FS) (Click to enlarge image) zamer na 210 mgz dlja 1 ADC -70 db protiv 3 ADC -74.5 db ######################################### http://www.eetimes.com/design/automotive-design/4009960/Multiple-A-Ds-versus-a-single-one-pushing-high-speed-A-D-converter-SNR-beyond-the-state-of-the-art This article shows how averaging the outputs of multiple high-speed ADCs can be used to improve data converter SNR. While an alternate technique of oversampling the input signal using faster ADCs is possible, the averaging approach seems preferable because faster ADCs which enable oversampling may not be available, and lower-speed ADCs used in an averaging approach may have better initial SNR specifications and lower power. As expected, the SNR of the system decreased as the input signal frequency was increased. The reason is that the clock signal jitter affects the aggregate SNR of the system, and the SNR reduction is dependent on the input signal frequency. This paper analyzed the effects of jitter internal and external to the ADCs, finding close agreement between experiment and theory. In summary, averaging the outputs of multiple ADCs can be used to improve state-of-the-art data converters. ADCs with low internal aperture jitter help maximize the SNR gain. With proper care taken with the input matching circuit and clock jitter, the SNR gains can match the 4.8 dB improvement predicted by theory when averaging three ADCs. About the Authors Grant Christiansen is an Engineering Manager at Texas Instruments, where he is lead for the signal-chain and digital power applications teams. He has four patents in read-channel applications and earned his MSEE from the University of Minnesota. Thomas Neu is a Field Applications Engineer for Texas Instruments, where he provides customer support with system and circuit designs. He received his MSEE in RF/Communication from Johns Hopkins University.
milstar: TI ADC dlja RLS iz rascheta nesuchaja 30 -70 mgz ,polosa 8 mgz (kak RLS w programme Apollo s dinamicheskim diapazonom bolee 120 db) ADS5485 16 bit /200 msps http://focus.ti.com/lit/ds/symlink/ads5485.pdf SNR 30mgz/70 mgz -75 db /75 db SFDR 30/70 mgz - 90 db/87 db IMD 29.5/30.5 mgz 69.5/70.5 mgz -95.9 dbfs/95.2 dbfs ENOB -12.1 bit na 10 mhz ADS5474 ,14 bit 400 msps http://focus.ti.com/lit/ds/symlink/ads5474.pdf SNR 30mgz/70 mgz/230 mgz -70.3 db /70.2db/69.8 db SFDR 30/70 mgz/230 mgz - 90 db/87/80 db IMD 69.5/70.5 mgz -93 dbfs ENOB -11.2/10.9 bit na 70/230 mhz
milstar: Powtor With stretch processing we are limited to a range extent that is usually smaller than a pulse width. ############################################################## Thus, we couldn’t use stretch processing for search because it requires looking for targets over a large range extent, usually many pulse widths long. ################## We could use stretch processing for track because we already know range fairly well but want a more accurate measurement of ################################################################################### it. We must point out that, in general, wide bandwidth waveforms, and thus the need for stretch processing, is “overkill” for tracking. Generally speaking, bandwidths of 1s to 10s of MHz are sufficient for tracking #################################################### Stretch processing does not relieve the bandwidth requirements on the rest of the radar. ########################################################## Specifically, the transmitter must be capable of generating and amplifying the wide bandwidth signal, the antenna must be capable of radiating the transmit signal and capturing the return signal, and the receiver must be capable of heterodyning and amplifying the wide bandwidth signal. This poses stringent requirements on the transmitter, antenna and receiver but current technology has advanced to be point of being able to cope with the requirements. stretch processor has the same range resolution as a matched filter. ########################################### Thus, the stretch processor encounters a SNR loss of relative to the matched filter. This means that we should be careful about using stretch processing for range extents that are a significant part of the transmit pulse width. www.ece.uah.edu/courses/material/EE710-Merv/Stretch.doc
milstar: http://www.ll.mit.edu/publications/journal/pdf/vol12_no2/12_2radarsignalprocessing.pdf Digital Signal Processing The development of digital signal processing for radar at Lincoln Laboratory provides a classic example of interdisciplinary technology transfer. The key realization of the potential for digital signal ##################################### processing in radars was the understanding that ballistic-missile-defense radars are pulsed systems ------------------------------------------------------------- and, unlike analog signal processing, the digital signal processing did not need to be time synchronous. If raw data are digitized [36] and stored in memory, the available processing time is the time until the next measurement, ----------------------------- not the real-time extent of the measurement itself.
milstar: opredelenija Raytheon Stretch Processing.Stretch processing is a technique frequently used to pro- cess wide bandwidth linear FM waveforms. The advantage of this technique is that it allows the effective IF signal bandwidth to be substantially reduced, allowing digitiza- tion and subsequent digital signal processing, at more readily achievable sample rates. By applying a suitably matched chirp waveform to the receiver first LO, coincident with the expected time of arrival of the radar return, the resultant IF waveform has a significantly reduced bandwidth for targets over a limited range-window of inter- est. Provided that the limited-range window can be tolerated, a substantially reduced processing bandwidth allows more economical A/D conversion and subsequent digital signal processing. It also allows a greater dynamic range to be achieved with lower- rate A/D converters than would be achievable if digitization of the entire RF signal bandwidth were performed. If the LO chirp rate is set equal to the received signal chirp rate of a point target, the resultant output is a constant frequency tone at the output of the stretch processor receiver, with frequency∆tB/T, where∆t is the difference in time between the received signal and the LO chirp signal, andB/T is the waveform chirp slope (chirp bandwidth/ pulse width). Target doppler is maintained through the stretch processing, producing an output frequency offset equal to the doppler frequency, though the wide percentage bandwidth often used means that the doppler frequency can change significantly over the duration of the pulse. Ignoring the effect of target doppler, the required RF signal bandwidth is equal to the transmitted waveform bandwidth. Given the RF signal bandwidthBR, the received pulse widthTR, and the range interval∆T, the required LO reference waveform dura- tion is given by http://www.scribd.com/doc/17534054/Chapter-6-Radar-Receivers
milstar: Effect of Characteristics on Performance.Noncoherent pulse radar perfor- mance is affected by front-end characteristics in three ways. Noise introduced by the front end increases the radar noise temperature, degrading sensitivity, and limits the maximum range at which targets are detectable. Front-end saturation on strong signals may limit the minimum range of the system or its ability to handle strong interference. Finally, the front-end spurious performance affects the susceptibility to off-frequency interference. Coherent radar performance is even more affected by spurious mixer characteris- tics. Range and velocity accuracy is degraded in pulse doppler radars; stationary target cancellation is impaired in MTI (moving-target indication) radars; and range sidelobes are raised in high-resolution pulse compression systems. Modern radar systems are mostly designed to maxi- mize the linear operating region, with limiters used only to handle excessively large signals that inevitably exist under worst case conditions. Applications.The I/Q demodulator, also referred to as a quadrature channel receiver, quadrature detector, synchronous detector, or coherent detector, performs fre- quency conversion of signals at the IF frequency to a complex representation,I+ jQ centered at zero frequency. The baseband in-phase (I) and quadrature-phase (Q) signals are digitized using a pair of A/D converters providing a representation of the IF signal, including phase and amplitude without loss of information. The resulting digital data can then be processed using a wide variety of digital signal-processing algorithms, depend- ing on the type of radar and mode of operation. Processing such as pulse compression, doppler processing, and monopulse comparison, all require amplitude and phase infor- mation. The predominance of digital signal processing in modern radar systems has led to almost universal need for Nyquist rate sampled data. In many modern radar systems, digitalI andQ data is now generated using IF sampling followed by digital signal pro- cessing used to perform the baseband conversion as described in Sections 6.10 and 6.11. I/Q demodulators are still used, though their use is increasingly limited to wider band- width systems where A/D converters are not yet available with the required combination of bandwidth and dynamic range to perform IF sampling.
milstar: RADAR RECEIVERS 6.35 DC Offset.Small signals and receiver noise can be distorted by an offset in the mean value of the A/D converter output unless the doppler filter suppresses this component. False-alarm control in receivers without doppler filters is sometimes degraded by errors of a small fraction of the least significant bit (LSB), so correction is preferably applied at the analog input to the A/D. DC offsets can be measured using digital pro- cessing of the A/D converter outputs and a correction applied using D/A converters, as shown in Figure 6.13. DC offset correction can also be performed effectively in the digital domain, provided that the DC offset at the input of the A/D converter is not so large that it results in a significant loss of available dynamic range. Many of the I/Q demodulator errors described above are either reduced dramati- cally or eliminated using IF sampling. This, along with the reduction of hardware required, are the reasons that IF sampling (described in Sections 6.10 and 6.11) is becoming the dominant approach. 6.10 ANALOG-TO-DIGITAL CONVERTERS The high-speed A/D converter is a key component in receivers of modern radar sys- tems. The extensive use of digital signal processing of radar data has resulted in a demand for converters with both state-of-the-art sampling rates and dynamic range. Analog to digital converters transform continuous time analog signals into discrete time digital signals. The process includes both sampling in the time domain, convert- ing from continuous time to discrete time signals and quantization, converting from continuous analog voltages to discrete fixed-length digital words. Both the sampling and quantization process produce errors that must be minimized in order to limit the radar performance degradation. In addition, a variety of other errors such as additive noise, sampling jitter, and deviation from the ideal quantization, result in non-ideal A/D conversion. Applications.The conventional approach of using a pair of converters to digi- tize theI andQ outputs of an I/Q demodulator is, in many cases, being replaced by digital receiver architectures where a single A/D converter is followed by digital signal processing to generateI andQ data. Digital receiver techniques are described in Section 6.11. Although the dividing line is arbitrary and advancing with the state-of-the-art, radar receivers are often classified as either wideband or high dynamic range. Different radar functions put a greater emphasis on one or the other of these parameters. For example, imaging radars put a premium on wide bandwidth, whereas pulse doppler radars require high dynamic range. Because radars are often required to operate in a variety of modes with differing bandwidth and dynamic range requirements, it is not uncommon to use different types of A/D converter, sampling at different rates for these different modes. Data Formats.The most frequently used digital formats for A/D converters are 2’s complement and offset binary.10 The 2’s complement is the most popular method of digital representation of signed integers and is calculated by complementing every bit of a given number and adding one. The Gray code10 is also used in certain high-speed A/D converters in order to reduce the impact of digital output transitions on the performance of the A/D con- verter. The Gray code allows all adjacent transitions to be accomplished by the change of a single digit only. Delta-Sigma Converters.Delta-sigma converters differ from conventional Nyquist rate converters by combining oversampling with noise-shaping techniques to achieve improved SNR in the bandwidth of interest. Noise shaping may be either low- pass or bandpass depending on the application. Delta-sigma architectures provide poten- tial improvements in spurious-free dynamic range (SFDR) and SNR over conventional Nyquist converters where tight tolerances are required to achieve very low spurious performance. Digital filtering and decimation is required to produce data rates that can be handled by conventional processors. This function is either performed as an integral part of the A/D converter function or can be integrated into the digital downconversion function used to generate digitalI andQ data, as described in Section 6.11. Performance Characteristics.The primary performance characteristics of A/D converters are the sample rate or usable bandwidth and resolution, the range over which the signals can be accurately digitized. The resolution is limited by both noise and distortion and can be described by a variety of parameters.
milstar: Opredelenija Raytheon 2008 http://www.scribd.com/doc/17534054/Chapter-6-Radar-Receivers Sample Rate.Sampling of band-limited signals is performed without aliasing distortion, provided that the sample rate (fs) is greater than twice the signal bandwidth and provided the sig- nal bandwidth does not straddle the Nyquist fre- quency (fs/2) or any integer multiple (Nfs/2). In conventional baseband approaches, sam- pling is usually performed at the minimum rate to meet the Nyquist criteria. Since the basebandI and Q signals have bandwidths (B/2) equal to half the IF signal bandwidth, a sample rate just greater than the IF bandwidth is required (see Figure 6.14). For IF sampling, a frequency at least twice the IF bandwidth is required; however, oversampling is typically employed to ease alias rejection filtering and to reduce the effect of A/D converter quantization noise. IF sampling is often performed with the signal located in the second Nyquist region, as shown in Figure 6.15 or in higher Nyquist regions. Stated Resolution.The stated resolution of an A/D converter is the number of output data bits per sample. The full-scale voltage range of a Nyquist rate converter is given byVFS = 2N Q, whereN is the stated resolution andQ is the least significant bit (LSB) size. Signal-to-Noise-Ratio (SNR).SNR is the ratio of rms signal amplitude to rms A/D converter noise power. For an ideal A/D converter, the only error is due to quan- tization. Provided that the input signal is sufficiently large relative to the quantization size and uncorrelated to the sampling signal, the quantization error is essentially ran- dom and is assumed to be white. The rms quantization noise isQ/ 12 , and signal- to-quantization-noise ratio (SQNR) of an ideal A/D converter is given by SQNR(dB)= 6.02N+1.76 (6.37) Practical A/D converters have additional sampling errors other than quantization, including thermal noise and aperture jitter. Provided that these additional errors can be characterized as white, they can be combined with the quantization noise with a resulting SNR less than the theoretical SNR of the ideal converter. Because various A/D converter error mechanisms are dependent on input signal level and frequency, it is important to characterize devices over the full range of input conditions to be expected. The available signal-to-noise ratio of state-of-the-art high-speed A/D con- verters has been shown11 to fall off by one-bit (6 dB) for every doubling of the sample rate. Over-sampling of the signal followed by filtering and decimation provides an improvement of one half-bit (3 dB) in the achievable signal-to-noise-ratio for each doubling of the sample rate. Thus, for high dynamic-range applications, the best per- formance is achieved using a state-of-the-art A/D converter that has a maximum sample rate just sufficient for the application. Spurious Free Dynamic Range (SFDR).SFDR is the ratio of the single-tone sig- nal amplitude to the largest spurious signal amplitude and is usually stated in dB. Similar to SNR, the spurious performance of an A/D converter is dependent on the input signal frequency and amplitude. The frequency of spurious signals is also depen- dent on the input signal frequency with the highest values typically due to low order harmonics or their aliases. When using IF sampling with a significant over-sampling ratio (fs B/2), the worst spurious signals may be avoided by choosing the sample frequency relative to signal frequency such that the unwanted spurious signals fall outside the signal bandwidth of interest. If the worst case spurious can be avoided, the specified SFDR is less important than the levels of the specific spurious components that fall within the bandwidth of interest. Again, it is important to characterize devices over the range of expected operating conditions. The impact of A/D converter spurious signals on radar performance depends on the type of waveforms being processed and the digital signal processing being performed. In applications using chirp waveforms with large time-bandwidth products, spurious signals are less critical as they are effectively rejected in the pulse compression pro- cess because their coding does not match that of the wanted signal. In pulse doppler applications, spurious signals are of much greater concern because they can create components with doppler at a variety of frequencies that may not be rejected by the clutter filtering. Signal-to-Noise-and-Distortion Ratio (SINAD).SINAD is the rms signal ampli- tude to the rms value of the A/D converter noise plus distortion. The noise plus dis- tortion includes all spectral components, excluding DC and the fundamental up to the Nyquist frequency. SINAD is a useful figure of merit for A/D converters, but in digital receiver applications, where the worst spurious components may fall outside of the bandwidth of interest, it is not necessarily a key discriminator between competing converters for a specific application. Effective Number of Bits (ENOB).The term effective number of bits is often used to state the true performance of an A/D converter and has been stated in the literature11 in terms of SINAD and SNR, as given below. Consequently, it is important to differ- entiate between definitions when using this term. Two Tone Intermodulation Distortion (IMD).Two tone intermodulation distortion is also important in receiver applications. Testing is performed with two sinusoidal input signals of unequal frequency and levels set such that the sum of the two inputs does not exceed the A/D converter full-scale level. Similar to IMD for amplifiers, the most significant distortion is usually second order or third order IMD products. However, due to the complex nature of the distortion mechanism in A/D converters, the amplitude of IMD products is not easily characterized and predicted by the measurement of an input intercept point. Input Noise Level and Dynamic Range.Accurate setting of the A/D con- verter input noise level relative to the A/D converter noise is critical to achieving the optimum trade-off between dynamic range and system noise floor. Too high a level of noise into the A/D converter will degrade the available dynamic range; too low a level will degrade the overall system noise floor. Sufficient total noise should be applied to the A/D converter input to randomize or “whiten” the quantization noise. This can be achieved with rms input noise (s) equal to the LSB step size (Q). In addition, the input noise power spectral density should be sufficient to minimize the impact on system noise due to the A/D converter noise. The impact on overall noise due to quantization noise is given by7 ss s 22 2 2 112 = +Q s≥Q (6.40) Typical operating points are in the range ofs /Q= 2 tos /Q= 1, with corresponding noise power degradation due to quantization of 0.09 dB and 0.35 dB, respectively. In practice, the SNR of high-speed converters is often such that the noise of the A/D converter is significantly greater than the theoretical quantization noise. In addi- tion, the A/D converter input signal noise bandwidth may be significantly less than the Nyquist bandwidth. This is a significant factor in IF sampling applications where the IF noise bandwidth is often less than ¼ of the Nyquist bandwidth. In this case, the total input and A/D converter noise must be sufficient to whiten the quantization noise, and the power spectral density of the input noise should be sufficiently greater than that of the A/D converter, as illustrated in Figure 6.16. In some cases, out-of-band noise may be added to whiten the A/D converter quantization noise and spurious signals. The out- of-band noise is then rejected through subsequent digital signal processing. A/D Converter Sample Clock Stability.The stability of the sample clock is critical to achieving the full capability of an A/D converter. Sample-to-sample varia- tion in the sampling interval, called aperture uncertainty or aperture jitter, produces a sampling error, proportional to the rate of change of input voltage. For a sinusoidal input signal, the SNR due to aperture uncertainty alone is given by12 SNR(dB)=−20log10(2p fsj) (6.43) wheref= input signal frequency sj=rms aperture jitter Similarly, close-to-carrier noise sidebands present on the sample clock signal are transferred to sidebands on the sampled input signal, reduced by 20log10 (f /fS ) dB. For example, in an IF sampling application with the input signal ¾ of the sample frequency, the close-to-carrier phase noise of the sample clock will be transferred to the output of the A/D converter output data signal, reduced by 2.5 dB
milstar: 6.11 DIGITAL RECEIVERS The availability of high-speed analog-to-digital converters capable of direct sam- pling of radar receiver IF signals has resulted in the almost universal adoption of digital receiver architectures over conventional analog I/Q demodulation. In a digital receiver, a single A/D converter is used to digitize the received signal, and digital signal processing is used to perform the downconversion toI andQ baseband sig- nals. Continuing advances in sampling speeds are leading to sampling at increasing frequencies, sometimes eliminating the need for a second downconversion, with the possibility approaching of sampling directly at the radar RF frequency. The benefits of IF sampling over conventional analog I/Q demodulation are ●Virtual elimination ofI andQ imbalance ●Virtual elimination of DC offset errors ●Reduced channel-to-channel variation ●Improved linearity ●Flexibility of bandwidth and sample rate ●Tight filter tolerance, phase linearity, and improved anti-alias filtering ●Reduced component cost, size, weight, and power dissipation The use of a high IF frequency is desirable as it eases the downconversion and filtering process; however, the use of higher frequencies places greater demands on the performance of the A/D converter. Direct RF sampling is considered the ulti- mate goal of digital receivers, with all the tuning and filtering performed through digital signal processing. The advantage being the almost complete elimination of analog hardware. However, not only does the A/D converter have to sample the RF directly, but unless it is preceded by tunable RF preselector filters, the A/D converter input must have the dynamic range to handle all of the signals pres- ent in the radar band simultaneously. Generally, the interference power entering the A/D converter is proportional to the bandwidth of components in front of the A/D converter. The required A/D converter SNR to avoid saturation on the interfer- ing signals is given by The crest factor is the peak level that can be handled within the full-scale range of the A/D converter relative to the rms interference level. It is set to achieve a sufficiently high probability that full-scale will not be exceeded. For example, with gaussian noise, a crest factor of 4 sets the peak level at the 4s level (12 dB above the rms level) with a probability of 0.999937 that the full-scale is not exceeded on each A/D converter sample. Setting the system noise level power spectral density into the A/D converterR(dB) above the A/D converter noise give The generation of basebandI andQ signals from the IF sampled A/D converter data is performed using digital signal processing and can be implemented through a variety of approaches.7 Two approaches are described next. Digital Downconversion.The digital downconversion approach is shown in Figure 6.17. The signal is sampled by the A/D converter, frequency shifted to base- band, low-pass filtered, and decimated to produce I/Q digital data. The signal spectrum at each stage of the process is shown in Figure 6.18. In continuous-time (Fig. 6.18a), frequency is in hertz and is represented byF. In discrete-time (Fig. 6.18b–e), fre- quency is in radians per sample and is represented byw. The spectrum of the ana- log input signalx(t) is shown in Figure 6.18a, with the signal spectrum centered at F0hertz. The signal is sampled by the A/D converter at frequency Fs, producing the time sequence x n ( )and frequency spectrum X( ) ωcentered at frequencyw0 with the image centered at−w0. The A/D converter output signal is then frequency shifted by complex multiplication with the reference signalej n −w0, corresponding to a reference signal rotating atw0 radians per sample, centering the signal spectrumX( ) wabout zero. The unwanted image is re-centered at−2w0 ifw0> p /2 or−2w0+ 2p ifw0≤ p /2. The unwanted image is then rejected using the FIR filter with impulse responseh(n) producing outputˆ( ) x n with spectrumˆ( ) Xw. Finally, the sample rate is reduced by RADAR RECEIVERS 6.45 provide the desired stopband rejection response. Thekth order CIC filter for decima- tion factorD has transfer function: Hz z zz K m mD K DK ( )= =−− − =− −− ∑01 1 11 (6.49) A polyphase filter is a filter bank that splits an input signal intoD sub-band filters operating at a sample rate reduced by a factorD, providing a computationally efficient approach to performing the FIR filtering followed by decimation in a digital receiver. Rather than computing all the filter output samples and only using everyDth sample, the polyphase approach calculates only those that are actually used. Figure 6.22 and Eq. 6.50 define how the filter with impulse responseh(n), followed with decimation by factorD, is implemented in a polyphase structure. The input signalx(n) is divided intoD parallel paths by the “commutator,” which outputs samples in turn, rotating in a counterclockwise direction, to each of the FIR filters operating at the reduced sample rate. The outputs of the FIR filters are summed to produce the output signaly(m). This architecture is beneficial as it provides an approach that can be easily parallelized at rateFX /D. pk(n) = h(k+ nD) k= 0, 1, …,D- 1 (6.50) n=0, 1, …, K-1 Multi-Channel Receiver Considerations.Modern radar systems rarely con- tain only one receiver channel. Monopulse processing, for example, requires two or more channels to process sum and delta signals. Additionally, the channels must be coherent, synchronized in time, and well matched in phase and amplitude. Digital beamforming systems require a large number of channels with similar coherence and synchronization requirements and tight phase and amplitude track- ing. The coherence requirement dictates the relative phase stability of LO and A/D converter clock signals used for each receive channel. The time synchroniza- tion requirement means that A/D converter clock signals for each channel must be aligned in time and decimation must be performed in phase for each channel. Phase and amplitude imbalance between channels is a result of variation in the http://www.scribd.com/doc/17534054/Chapter-6-Radar-Receivers opredelenija raytheon
ïîëíàÿ âåðñèÿ ñòðàíèöû