Ôîðóì » Äèñêóññèè » Operazionnie ysiliteli ,ZAP/AZP & (ïðîäîëæåíèå) » Îòâåòèòü
Operazionnie ysiliteli ,ZAP/AZP & (ïðîäîëæåíèå)
milstar: 1941: First (vacuum tube) op-amp An op-amp, defined as a general-purpose, DC-coupled, high gain, inverting feedback amplifier, is first found in US Patent 2,401,779 "Summing Amplifier" filed by Karl D. Swartzel Jr. of Bell labs in 1941. This design used three vacuum tubes to achieve a gain of 90dB and operated on voltage rails of ±350V. ###################################################### It had a single inverting input rather than differential inverting and non-inverting inputs, as are common in today's op-amps. Throughout World War II, Swartzel's design proved its value by being liberally used in the M9 artillery director designed at Bell Labs. ######################################################################### This artillery director worked with the SCR584 radar system to achieve extraordinary hit rates (near 90%) that ####################################################################### would not have been possible otherwise.[3] ########################### http://en.wikipedia.org/wiki/Operational_amplifier
milstar: Adding the HMC660LC4B Track-and-Hold Amplifier to a lower bandwidth ADC allows the ADC to subsample a fairly broadband signal (for example, 1 GHz centered at 3.5 GHz) and then directly convert (or alias) it to baseband frequency for conversion by a lower-speed, high-resolution ADC. When used with lower sample rate converters, the HMC660LC4B can provide an extension of input sampling bandwidth. When used with higher sample rate converters, the THA can provide improved high frequency linearity. For example, the linearity of even the highest speed, state-of-the-art AT84AS008 Atmel converter starts to significantly degrade above 2 GHz, and linearity is not specified above this frequency, even though the device supports an input bandwidth of 3.3 GHz. Since the full-scale input for this converter is 0.5 Vpp, the HMC660LC4B would operate at half-full-scale in this application (SFDR ~60 dB or better over the input band) and could provide both a bandwidth extension to 4.5 GHz, as well as improved high frequency linearity when used with this type of converter. http://www.mpdigest.com/issue/Articles/2007/apr/Hittite/Default.asp
milstar: Schetwerennie wisokoskorostnie ADC http://www.e2v.com/assets/media/files/documents/broadband-data-converters/doc1002B.pdf
milstar: Military and space The military and space industries tend to favor high-speed ADCs reaching high-sampling frequencies beyond GSPS, using a single-core architecture and no hidden internal interleaving. ------------------------------------- It is known that interleaving ADC cores in systems that are subject to wide temperature swings requires temperature monitoring and management of calibration and re-calibration each time the system is subject to significant temperature changes (see Ref 1). Therefore, data converters that achieve GSPS sampling rates with a single high-speed core and thus without using any interleaving techniques show nominal performance across their full temperature range without having to manage calibrations and without using FPGA processing power to remove interleaving spurs in the digital domain. The contract awarded by the European Space Agency to e2v technologies to develop a 10-bit 1.5 GSPS (see Ref 2) will result in a data converter specifically designed to meet the requirements of the space industry and will indeed reach 1.5 GSPS without any internal interleaving and still meet low-power requirements. The military industry welcomes both high-input frequencies and high-sampling rates without internal interleaving for the same reasons of performance across temperature range explained above. They are users of devices such AT84AS004, EV10AS150 and similar devices. The GSPS data conversion industry is an area where CMOS and bipolar technologies still compete to some extent. The recent designs from e2v on both Infineon B7HF200 full bipolar process and Jazz Semiconductor high-speed BiCMOS processes achieve power consumption levels that are comparable to CMOS GSPS data converters, but with higher input bandwidths typical of fast bipolar technologies. Reduced supply current transients — such as with e2v’s EV10AQ190 and ADC cores — which can sample signals as fast as 2.5 GSPS without the use of any form of internal interleaving (such as e2v’s EV10AS150). On the other side, CMOS devices typically have a power consumption that is proportional to the sampling frequency and thus the nominal power consumption is reduced in applications where the ADC clock can be slowed down. 10-bit GSPS ADC-overview 10-bit GSPS ADC Typical Power consumption overview. Source: Suppliers datasheets published on their respective Web sites. 10-bit ADCs: • EV10AQ190 Quad 10-bit 1.25-GSPS device from e2v technologies. BiCMOS process technology from Jazz Semiconductor; power consumption per channel sampling at 1.25 GSPS: 1.4 W /channel at 1.25 GSPS. • ADC10D1000 dual 10-bit 1-GSPS ADC from National Semiconductor. Supplier’s own CMOS Process technology; power consumption per channel sampling at 1 GSPS: 2.77 W in total for 2 channels enabled or 1.61 W for single channel enabled. For the foreseeable future, the choice of standard GSPS ADCs will continue to increase with a combination of additional integrated features, higher sampling rates and higher input bandwidths accommodating input signals frequencies well into the S-Band. http://www2.electronicproducts.com/PrintArticle.aspx?ArticleURL=facn_e2V_oct2009.html more and more stringent — sampling rates, input frequencies and resolution all tend to increase. Also, despite an exciting performance competition between today’s best amplifier manufacturers, high-speed differential amplifiers are already a limiting factor in terms of bandwidths, especially with system resolutions of 10 bits designed to digitize signals frequencies in the L-band and beyond. In these applications, only balun transformers provide the appropriate ADC input driver performance. Unfortunately, dc coupling is not possible when transformers are used as differential ADC input drivers. So, as of today, designers of high-speed and high-frequency data conversion systems need to make a choice for each channel between dc coupling but with limited bandwidths — typically up to 1 GHz, depending on the chosen amplifier and its operating conditions — and high input frequencies (but only in ac-coupling mode). Typically, high-speed amplifiers demonstrate best harmonic-distorsion performance versus frequency with reduced output voltage swings (see Ref. 3). Thus, applications that require dc coupling at the highest possible input frequency will benefit from selecting an ADC with reduced input-voltage range, since this will translate directly into a reduced output voltage swings for the differential amplifiers.
milstar: Sandia patent 8 bit flash Max108 w SAR http://www.freepatentsonline.com/6864827.html http://www.freepatentsonline.com/6864827.pdf ADC sample rate (chastota diskretizacii) -1 ghz Maximum IF polosa -222 mgz Minimum -3.5 mgz 1 IF/Pch -4000 mgz 2 IF/Pch -250 mgz SAR receiver employing strech processing ############################ (RF bandwitch compression or deramp mixing) MAX108 SNR -46.9db ,1 gigasample ,125-375 mgz signal ,full input ENOB-7.5 bit SFDR 60 db THD -53 db worst case 125 mgz -375 mgz Dannij patent werojatno ispolzowan w SAR Sandia ,snimki woennoj texniki s razr. 100 mm nize http://www.youtube.com/watch?v=aPgLx476TlQ&feature=related Lt. Col. Brandon Baker, commander of Detachment 3, 9th Operations Group, recaps preparations made at Andersen Air Force Base, Guam, for the arrival of assigned Global Hawk Remotely Piloted Aircraft (RPAs) later in 2010. ##################################################################### W broschure po Global Hawk RQ-4 block 20 http://www.as.northropgrumman.com/products/ghrq4b/assets/GH_Brochure.pdf rasreschajuschaj sposbmsot Radara danna - 1/ 0.3 metra na linke Sandia Lab snimki s razreschajuschej sposonostju 10 santimetrow #################### Mozete posmotret http://www.sandia.gov/RADAR/images/ka_band_portfolio.pdf Rjad video s raschreschajuschej sposobnostju 30 santimetrow i 1 metr tam ze http://www.sandia.gov/RADAR/movies.html ################################### Automatic Target Recognition http://www.sandia.gov/atr/ Scalable Real-Time System ATR real-time requirements include both high throughput rate and low latency. For conventional image sizes, the latency between receipt of the SAR image and ATR results is typically less than 10 seconds. The basic configuration of our all-COTS real-time ATR has 12 PowerPC 300 MHz CPUs and can process imagery at the rate of one Megapixel per second for 10 targets of interest. The CPU requirements of our ATR system scale linearly with respect to pixel rate and number of targets. The 6U VME rack shown above can accommodate 64 CPUs, which enables us to upgrade the system to allow data rates as high as five Megapixels per second for 10 targets of interest or 50 targets of interest at one Megapixel per second without changing the 3.5 ft3 size of the ATR system. Upcoming advances in CPU performance will triple our current capabilities by the end of the year 2000. ------------------------ ATR Experience Sandia's Signal and Image Processing Department has designed ATR algorithms for SAR sensors since 1986. We were the first to demonstrate real-time SAR ATR capability in 1991, on board the Department of Energy's De Havilland DHC-6 Twin Otter aircraft. Since then, Sandia has been the leader in SAR ATR technology, integrating the latest hardware with innovative recognition algorithms. ######################################## ABSTRACT This paper describes the Twin-Otter SAR Testbed developed at Sandia National Laboratories. This SAR is a flexible, adaptable testbed capable of operation on four frequency bands: Ka, Ku, X, and VHF/UHF bands. The SAR features real-time image formation at fine resolution in spotlight and stripmap modes. High-quality images are formed in real time using the overlapped subaperture (OSA) image-formation and phase gradient autofocus (PGA) algorithms. http://www.sandia.gov/RADAR/files/igarss96.pdf
milstar: Signal processing deep space array network http://tmo.jpl.nasa.gov/progress_report/42-157/157N.pdf IF/pch -1280 mgz ,polosa 500 mgz x -8-8.8 ghz i Ka band 31-38 ghz array signal processing subsystem polosa 500 mgz ,zentr pch 950 mgz ispolzuetsja ATmel 10 bit 2 gsps http://www.datasheetarchive.com/pdf-datasheets/Datasheets-319/61540.html
milstar: http://microelectronics.esa.int/amicsa/AMICSA_2006/5.2.bellin.pdf ocenka AT84sa008 kosmicheskie primenenija
milstar: New Products 10bit 2.5Gs/s ADCs for high RF sampling applications October 16, 2009 | | 220601094 e2v, has announced production of a 10bit 2.5Gs/s analog to digital converter (ADC) incorporating 5GHz analog input bandwidth for operation over the L-band and S-band frequencies. Chelmsford, UK - e2v, has announced production of a 10bit 2.5Gs/s analog to digital converter (ADC) incorporating 5GHz analog input bandwidth for operation over the L-band and S-band frequencies. The EV10AS150ATP ADC is being exhibited at the International Radar Conference, RADAR'09 in Bordeaux, France. This device's high sampling rate of 2.5Gs/s suits it to applications such as high speed test instrumentation, automatic test equipment (ATE), high speed data storage, software defined radio, radar and flight simulators and wideband satellite receivers. The company points out that the device will enable designers to process 1GHz of IF analogue signal, without needing multiple down-conversion stages. The EV10AS150ATP series – the first in a family of pin-compatible 10bit ADCs – boasts a spurious free dynamic performance of 60dB and 52dB signal to noise ratio (SNR). According to e2v, IMD3 is 60dBc, whilst it's effective number of bits (ENOB) is 8.1bits. The EV10AS150ATP, which comes in a EBGA 317 pin package (25 x 35mm) is made using Infineon's high-speed bipolar SiGe silicon technology, with both commercial and industrial grade versions now available. e2v wins ESA's ADC contract
milstar: http://www.alcom.be/binarydata.aspx?type=doc/e2V_EV10AS150A.pdf Features • ADC 10-bit Resolution • Up to 2.5 Gsps Sampling Rate • Selectable 1:4 or 1:2 Demultiplexed Digital LVDS Outputs • True Single Core Architecture (No Calibration Required) • External Interleaving Possible Via 3-Wire Serial Interface – Gain Adjust – Offset Adjust – Sampling Delay Adjust • Full Scale Analog Input Voltage Span 500 mVpp • 100Ω Differential Analog Input and Clock Input • Differential Digital Outputs, LVDS Logic Compatibility • Low Latency Pipeline Delay • Test Mode for Output Data Registering (BIST) • Power Supplies: 5.0V, 3.3V, 2.5V • Power Management (Nap, Sleep Mode) • EBGA317 (Enhanced Ball Grid Array) Package Performance • Single Tone Performance in 1st Nyquist (–1 dBFS) – ENOB = 7.7 bit, SFDR = –56 dBFS at 2.5 Gsps, Fin = 500 MHz – ENOB = 7.8 bit, SFDR = –58 dBFS at 2.5 Gsps, Fin = 1245 MHz • Single Tone Performance in 2nd Nyquist (–3 dBFS): – ENOB = 8.0 bit, SFDR = –60 dBFS at 2.5 Gsps, Fin = 2495 MHz • 5 GHz Full Power Input Bandwidth (–3 dB) • ±0.5 dB Band Flatness from 10 MHz to 2.5 GHz • Input VSWR = 1.25:1 from DC to 2.5 GHz • Bit Error Rate: 10–12 at 2.5 Gsps • No Missing Codes at 2.5 Gsps, 1st and 2nd Nyquist Screening • Temperature Range – Commercial “C” Grade: Tamb > 0°C ; TJ < 90°C – Industrial “V” Grade: Tamb > –40°C ; TJ < 110°C Applications • Direct Broadband RF Down Conversion • Wide Band Communications Receiver • High Speed Instrumentation • High Speed Data Acquisition Systems 1. Block Diagram The EV10AS150A combines a 10-bit 2.5 Gsps fully bipolar analog-to-digital converter chip, driving a fully bipolar DMUX chip with selectable Demultiplexing ratio (1:2) or (1:4). The 5 GHz full power input bandwidth of the ADC allows the direct digitization of up to 1 GHz broadband signals in the high IF region, in either L_Band or S_Band. The EV10AS150A features 7.8 effective bit and close to –58 dBFS spurious level at 2.5 Gsps over the full 1st Nyquist for large signals close to ADC Full Scale (–1 dBFS), and 8.0 Bit ENOB at –3 dBFS in the 2nd Nyquist zone. The 1:4 demultiplexed digital outputs are LVDS logic compatible, which allows easy interface with standard FPGAs or DSPs. The EV10AS150A operates at up to 2.5 Gsps in DMUX 1:4 and up to 2.0 Gsps in 1:2 DMUX ratio (The speed limitation with 1:2 DMUX ratio is mainly dictated by external data flow exchange capability at 2 × 1 Gsps with available FPGAs). The EV10AS150A ADC+DMUX combo device is packaged in a 25 × 35 mm Enhanced Ball Grid Array EBGA317. This Package is based on multiple layers which allows the design of low impedance continuous ground and power supplies planes, and the design of 50Ω controlled impedance lines (100Ω differential impedance). This package has the same Thermal Coefficient of Expansion (TCE) as FR4 application boards, thus featuring excellent long term reliability when submitted to repeated thermal cycles. Power dissipation do 8 watt clock jitter do 120 femtosec (internal)
milstar: IF undersampling The IF undersampling technique has long been sought as a means for reducing the complexity of a receiver design. In fact, sampling as close to the antenna as possible offers the possibility of reducing the size and complexity of the receiver function in a system. Most modern cellular base stations implement IF sampling allowing one or more IF stages to be eliminated from their system reducing both cost and complexity. While IF undersampling does reduce overall system cost, there is a performance trade off in that IF undersampling ADCs in the past have generally resulted in lower performance than baseband sampling ADCs. ######################################################### Over the past few years, this requirement has driven the demand for high-performance IF sampling ADCs and are now available that are optimized for SNR and SFDR for frequencies as high as 450 MHz. http://mobiledevdesign.com/software_design/radio_understanding_state_art/index1.html
milstar: Sample rate Sample rates are driven by several factors. The largest driver is to have a sample rate that is an integer multiple of common data rates for communication standards. For example, CDMA2000 has a base symbol rate of 1.2288 MHz, WCDMA has a base rate of 3.84 MHz and TD-SCDMA has a base rate of 1.28 MHz. Based on these rates, common sample rates of 78.6, 92.16, 122.88 and 245.76 megasamples per second (Msps) are common. As in the past, the ADC technology determines the preferred sample rate. And over the past few years, the preference is to run above 80 Msps in most new designs. Higher sample rates do improve noise performance of ADCs. While the overall integrated noise does not improve, the distribution of the noise over wider bandwidths does offer improvements in noise spectral density (NSD). The lower the noise spectral density, the more sensitive a receiver can be designed. This process is often referred to as processing gain and is nothing more than distributing the same noise over a wider band of frequencies and then digitally filtering out the noise in the frequency bands that are not of interest. Doubling the sample rate can improve the noise spectral density by a factor of 3 dB resulting in a significant improvement in performance of many systems. However, there are limits to how much sample rates can be increased. Current FPGA[1] and ASIC[1] technology limits CMOS[1] data rates to about 250 MHz, LVDS[1] to approximately 800 MHz and PECL[1] to approximately 1.5 GHz. Other logic schemes such as CML[1] offer the possibility of even higher rates. While some applications have moved to LVDS and PECL, the bulk of applications are implemented in CMOS. This will change in the future, but for now, the mainstream driving applications are still CMOS.
milstar: primer priemnik s prjamoj podachej RF signala na wxod AZP http://winradio.com/home/g31ddc.htm 9 kHz to 49.995 MHz continuous frequency range Direct sampling Digital down-conversion 16-bit 100 MSPS A/D conversion 50 MHz-wide, real-time spectrum analyzer 2 MHz recording and processing bandwidth Three parallel demodulator channels Waterfall display functions Audio spectrum analyzer Audio and IF recording and playback Recording with pre-buffering EIBI, HFCC and user frequency databases support Very high IP3 (+31 dBm) Excellent sensitivity (0.35 µV SSB, 0.16 µV CW) Excellent dynamic range (107 dB typ.) Selectable medium-wave filter USB 2.0 interface dlja srawnenija priemnik toj ze firmi no s F/promezutochnoj chastotoj http://winradio.com/home/g313e.htm The WiNRADiO WR-G313e is a software-defined high-performance HF receiver (9 kHz to 30 MHz, optionally extendable to 180 MHz) with a USB interface, an external version of the acclaimed WR-G313i receiver. The receiver is extremely sensitive, making it possible to comfortably read CW signals under 0.05 µV input levels, yet featuring a respectable 95 dB dynamic range making the receiver resistant to strong signal overload. The high sensitivity is also matched by that of the S-meter: The fully calibrated S-meter shows the received signal levels in dBm, µV or S-units, down to the ‑140 dBm noise There are numerous demodulation modes, continuously variable IF bandwidth 1 Hz to 15 kHz (in 1 Hz increments), a 20 kHz wide real-time spectrum analyzer with 16 Hz resolution, noise blanker and notch filter. There is also an integrated recorder, making it possible to instantly record and playback the received signal. Apart from audio recording and playback, the receiver can also record an entire 20 kHz wide IF spectrum, making it possible to thoroughly analyze the received signal, and "re-receive" the same signal again and again with different IF filter bandwidths, notch filter, noise blanking or demodulator settings, to arrive at the best possible reception of weak or interference-prone transmissions. In addition to the real-time narrow-band spectrum analyzer, there is also a wide-band spectrum analyzer which contains additional professional instrumentation facilities: the ability to display minimum and maximum spectrum sweeps, search for peaks, average spectra, save and print spectra, marker mode, etc. Another useful feature, previously unavailable with receivers of this price class, is a test and measurement facility, performing measurements on the received signal including frequency accuracy, amplitude modulation depth, frequency deviation, THD (total harmonic distortion) and SINAD. An audio spectrum analyzer is also included, making it possible to observe the demodulated spectrum in real-time with a resolution of 5 Hz.
milstar: Stat*ja Triquint (GaAS dlja Radarow ,kommunikazij) i Watkins Johnson o dinamicheskom diapazone priemnikow https://www.triquint.com/prodserv/tech_info/docs/WJ_classics/vol14_n1.pdf https://www.triquint.com/prodserv/tech_info/docs/WJ_classics/vol14_n2.pdf http://www.triquint.com/prodserv/tech_info/docs/WJ_classics/vol14_n1.pdf http://www.triquint.com/prodserv/tech_info/docs/WJ_classics/vol14_n2.pdf
milstar: Powtor Linkoln laboratory Radar open system architecture A High Dynamic Range Receiver for the Radar **************************************** Open System Architecture 2008 X-Band Receiver The MITEQ X-Band receiver is of a dual conversion superheterodyne architecture that translates a 10 GHz signal with a bandwidth of 1 GHz to an IF center frequency of 70 MHz and a bandwidth of 20 MHz for stretch processing of radar returns. The receiver also includes a wideband IF output at 1 GHz for use with advanced high speed ADC (analog to digital converter) processing techniques such as optical processing, time sequenced ADC arrays, or time stretched ADC arrays http://highfrequencyelectronics.com/Archives/May08/HFE0508_Cannata.pdf 1.Peak Pulse Detection and Delayed AGC A built-in SDLVA (successive detection log video amplifier) provides detection of the filtered IF output signal over an 80 dB dynamic range, ------------ and an on-board ADC digitizes the video signal and performs peak detection within a gate (or windowing) pulse signal provided by the radar platform. The resulting peak is read by the system between pulses, which subsequently commands the on-board gain control over the VMEbus to set the receiver’s sensitivity for the next pulse, a process commonly referred to as delayed AGC. ----------------------------------- 2.Digitally Calibrated Attenuator Gain control for the receiver is provided by a voltage-controlled microwave attenuator. The attenuator attenuator is driven by an on-board DAC (digital to analog converter). The attenuator provides 40 dB of additional ---------------------------------------------- dynamic range for the receiver, and is capable of being set prior to reception of each radar pulse to optimize the dynamic range of the system. As the target approaches, the system will sense higher peak signal strength, and then reduce the receiver’s gain.
milstar: High-Dynamic-Range Receivers for Digital Beam Forming Radar Systems Keir C. Lauritzen, Joseph E. Sluz, Matthew E. Gerwell, Albert K. Wu, and Salvador H. Talisa, The Johns Hopkins University Applied Physics Laboratory, 11100 Johns Hopkins Road Laurel, MD 20723 http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4250284 V. CONCLUSION (ST-SFDR) for the 1.0-dB receiver configuration. As with The S-Band receiver made allowed the study of the issues two-tone measurements, the FE was not used but the expected that limit dynamic range. This study included the detailed noise output based on the gain and noise figure of the FE is measurement of spurious content well below the noise of the indicated on the plot by the orange line. The ma*genta points rreecceei1vveerr ttoo gzaai1nn 1~nsight on the dynamic range limitations that are measured noise levels without the FE. Our measurements might exist in a DBF system if these spurs were correlated. allowed close observation of spurs well below the noise. Future work will include SFDR measurements using several Some of the harmonics shown are not within the 15 1\/IVIz receivers like the one described here and an investigation of bandwidth for this input frequency but would be in band for correlation of noise and spurs among receivers.
milstar: powtor 2008 105 db 16 bit razreschenie http://highfrequencyelectronics.com/Archives/Nov08/1108_Friedman.pdf A Wide Dynamic Range Playback System for Radar Signals This article describes the use of a dual high-speed 16-bit DAC for reproducing a Doppler weather radar signal. The signal is played back from a digital recording produced using the digitizer described in the preceding article. A simplified block diagram for the system is shown in Figure 1. Note that the dual 16-bit DAC is used to effectively emulate a 20- bit DAC by the means described in this article. This system is required to digitally record and reproduce an analog reflection-return radar signal down-converted to an IF of 30 MHz in a 1-MHz bandwidth. A key requirement is the ability to accommodate a dynamic range of at least 105 dB between the maximum- capable and minimum-detectable amplitudes that may occur in the course of a single radar trace. The actual system operates above 5 GHz and includes RF mixers, filters, amplifiers, tunable frequency sources, and other analog devices that are not shown in the figure. However, the dynamic range and SNR are set primarily by the IF devices in this diagram ############################ t.e. ADC
milstar: powtor k stat'e wische http://highfrequencyelectronics.com/Archives/Sep08/HFE0908_S_Crean.pdf A 16-bit ADC is used to capture the (C Band) transmit pulse after down conversion to IF. This adequately records the start pulse for synchronization and associated signal phase for demodulation. However, the input RF return signal has a dynamic range of 105 dB, which is greater than the (ideal theoretical) dynamic range for any commercial, high-speed ADC (limited to 16 bits). This dynamic range requires a 20-bit ADC as shown. To provide this capability, the normal input signal range is extended using instantaneous automatic gain control (AGC) as part of the digital signal processing (DSP) function. ADC Dynamic Range An ideal ADC has an SNR equal to 6.02 × N + 1.76 dB, where N is equal to the number of bits. For a 16-bit converter, this translates to 98 dB, which is the maximum (ideal theoretical) limit for input signal dynamic range. However, for high speed converters this ideal SNR is never achieved due to other issues which conspire to limit the SNR to a much lower value. These issues include ADC nonlinearity, front end amplifier noise and sample clock jitter. A typical SNR value for a high-speed (120 MHz sample rate) ADC is about 76 dB, which is well below the theoretical limit. For example, assume an input signal of 30 MHz and a required SNR of 80 dB. This, in turn, requires a clock with jitter of no more than 531 picoseconds. This assumes an ADC SNR that is much better than 80 dB, making jitter the limiting factor. Clocks and oscillators are often specified in terms of phase noise rather than timing jitter. The two are similar, and phase noise can be converted to jitter. Raltron offers a Web-based calculator [2] for this purpose Wide Dynamic Range Digitizing As mentioned previously, recording weather radar signals requires a minimum of 105 dB of dynamic range. Since the dynamic range of available high speed ADCs is limited to 90 dB (with processing gain), with further reductions down to 80 dB due to the clock source (jitter), a simple ADC is not sufficient. ############## Symtx Inc. has implemented a dual ADC scheme to increase digitizer dynamic range as shown in Figure 3. ################################### The design uses a high-gain channel to process low-level signals and a low-gain channel to process high-level signals, with simultaneous sampling of both channels in parallel. The gain difference between the high-level and low level ADCs is compensated with an appropriate n-bit left shift to give the correct scaling. ################## A DSP after the two ADCs then selects the correct ADC output, adjusts for gain, and merges the two to create a 20-bit word with the desired dynamic range. The process is essentially an instantaneous AGC which
milstar: ABOUT GMR office GMR Research & Technology in Acton, MA. GMR Research & Technology is a small, privately owned company located in Concord, Massachusetts and Acton, Massachusetts. Founded in March 2004 by Dr. Gil M. Raz, GMR is developing innovative nonlinear signal processing techniques to improve high-speed communications and surveillance systems. An example of the GMR innovations includes a proprietary method for parsimoniously achieving several orders of magnitude measured improvement in linear dynamic range for very wideband RF sensors. This method requires no changes in the analog front-end of the sensor system and is performed entirely in the digital domain after sampling. These results were achieved in collaboration with MIT - Lincoln Laboratory. This technology is currently funded to be inserted into sensor system platforms built at the Northrop Grumman Corporation. ----------------------------------------------------------------------------------------------------------- GMR is actively developing and securing intellectual property for solving problems difficult or intractable for traditional signal processing. GMR has several patents pending including one for its Non-Linear Affine Transform technique (NoLAff). http://gmrtech.com/about.html http://www.ll.mit.edu/HPEC/agendas/proc09/Day2/S4_1405_Song_presentation.pdf
milstar: 16 bit AD9467 250 msps i Fin do 300 mgz ne naschel nichego 18-22 bit 24 bit 4 msps . grafiki na fig 19 ,20 http://focus.ti.com/lit/ds/symlink/ads1675.pdf normirowan dlja Fin 1.6 mgz ( 1 pch w priemnikax s 2 preobraowaniem chastoti dlja diapazow do 30 mgz) dinamicheskij dipazon pri oversampling 32 -105 db ne silno lutsche chem y 16 bitnix s 160-250 msps pri pch 70 mgz i polose 20 mgz (93 db i bolee, s dither bolee 100 db )
milstar: http://pstca.com/pdfs/postproc.pdf this concept has been widely adopted in the test and measurement industry, particularly for wideband digital oscilloscopes. That it continues to make an impact in this market is evidenced by the 20-GSPS, 8-bit ADC that was recently developed by Agilent Labs3 and adopted by the Agilent Technologies Infiniium™ oscilloscope family.4 Advanced Digital Post-Processing Techniques Enhance Performancein Time-Interleaved ADC Systems By Mark Looney [mark.looney@analog.com] INTRODUCTION Time interleaving of multiple analog-to-digital converters by multiplexing the outputs of (for example) a pair of converters at a doubled sampling rate is by now a mature concept—first introduced by Black and Hodges in 1980.1
milstar: There are also other advantages gained by increasing sampling frequency. Over-sampling signals also enables processing-gain benefits in the digital domain with the use of digital filtering. This is because the ADC noise floor can be spread over a larger output bandwidth. Doubling the sampling rate, for a fixed input bandwidth, results in a 3 dB improvement in dynamic range. Every further doubling of the sampling frequency provides an additional 3 dB of dynamic range http://www.analog-europe.com/en/solutions_for_time_interleaving_ultra-high-speed_adcs_at_the_pcb_level?cmp_id=7&news_id=221601117 Figure 1 illustrates the benefit in doubling sampling frequency in an oscilloscope front-end. The 6 Gsps sampled waveform is a much more accurate representation of the sampled analog input. Many other test instrumentation systems, such as mass spectrometers and gamma ray telescopes, depend on high over-sampling to FIN ratios for pulse-shape measurement. Home » News » Full News Print - Send - - Technology News Solutions for time interleaving ultra-high-speed ADCs at the PCB level November 04, 2009 | | 221601117 This article explores the inherent technical challenges associated with time interleaving ADCs and provides useful system-design guidelines. -------------------------------------------------------------------------------- Synchronously sampling analog signals with time-interleaved analog/digital converters (ADCs) at billions of times per second is a considerable technical challenge, and requires very carefully designed mixed-signal circuits. In essence, the goal of time interleaving is to multiply the sampling frequency by the number of converters used, but without impacting resolution and dynamic performance. This article explores the inherent technical challenges associated with time interleaving ADCs and provides useful system-design guidelines. New and innovative component features and design techniques that address the known issues are presented. Measured FFT results from a 7 Gsps (gigasamples per second), two-converter chip 'interleaved solution' are provided. Finally, applications-support circuitry necessary to achieve high performance is described, including clock sources and drive amplifiers. Increasing need for higher sampling speeds When and why is it an advantage to increase sampling frequency? There are several answers to this question. Essentially an ADC's sampling speed directly determines the instantaneous bandwidth that may be digitized in one sampling instant. The Nyquist and Shannon sampling theorems state that the maximum available sampling bandwidth (BW) is equal to half the sample frequency (Fs). A 3-Gsps ADC enables 1.5 GHz analog-signal spectrum to be sampled in one sampling period. Doubling the sampling speed also doubles the Nyquist bandwidth to 3 GHz. The resultant multiplication in sampling bandwidth gained by time interleaving is beneficial in many applications. For example, radio-transceiver architectures can increase the number of information signal carriers, and therefore, system data throughput can be expanded. Increasing Fs also improves resolution in laser imaging detection and ranging (LIDAR) measurement systems, which operate on the principle of time of flight (TOF). The uncertainty in TOF measurements can be reduced by decreasing the effective sampling-clock period. Summary 2009 god The challenges associated with interleaving high-speed ADCs and several approaches to addressing these issues have been presented. Maintaining excellent dynamic performance beyond 6 Gsps is now possible due to advancements in interleaving methodologies, low-jitter clock sources and high-performance amplifiers. About the author Paul McCormack is a senior applications engineer in National Semiconductor Corporation's High-Speed Signal Path Group in Europe. He received his Masters degree in Electrical and Electronic Engineering from the Queen's University of Belfast.
ïîëíàÿ âåðñèÿ ñòðàíèöû